L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.1.1.3. Write Descriptor Controller Avalon-MM Master Interface

The Avalon-MM Descriptor Controller Master interface is a 32-bit single-DWORD master with wait request support. The Write Descriptor Controller uses this interface to write status back to the PCI-Express domain and possibly MSI when MSI messages are enabled. This Avalon-MM master interface is only available for the internally instantiated Descriptor Controller.

By default MSI interrupts are enabled. You specify the Number of MSI messages requested on the MSI tab of the parameter editor. The MSI Capability Structure is defined in Section 6.8.1 MSI Capability Structure of the PCI Local Bus Specification.

Table 31.   Write Descriptor Controller Avalon-MM Master interface

Signal Name

Direction

Description

wr_dcm_address_o[63:0]

Output

Specifies the descriptor status table or MSI address.

wr_dcm_byte_enable_o[3:0]

Output

Specifies which data bytes are valid.

wr_dcm_read_data_valid_i

Input

When asserted, indicates that the read data is valid.

wr_dcm_read_data_i[31:0]

Output

Specifies the read data for the descriptor status table entry addressed.

wr_dcm_read_o

Output

When asserted, indicates a read transaction.

wr_dcm_wait_request_i

Input

When asserted, indicates that the Avalon-MM slave device is not ready to respond.

wr_dcm_writedata_o[31:0]

Output

Specifies the descriptor status table or MSI address.

wr_dcm_write_o

Output

When asserted, indicates a write transaction.

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