L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

10.5.6. ebfm_cfgwr_imm_nowt Procedure

The ebfm_cfgwr_imm_nowt procedure writes up to four bytes of data to the specified configuration register. This procedure returns as soon as the VC interface module accepts the transaction, allowing other writes to be issued in the interim. Use this procedure only when successful completion status is expected.

Location

altpcietb_g3bfm_rdwr.v

Syntax

ebfm_cfgwr_imm_nowt(bus_num, dev_num, fnc_num, imm_regb_adr, regb_len, imm_data)

Arguments

bus_num

PCI Express bus number of the target device.

dev_num

PCI Express device number of the target device.

fnc_num

Function number in the target device to be accessed.

regb_ad

Byte-specific address of the register to be written.

regb_ln

Length, in bytes, of the data written. Maximum length is four bytes, The regb_ln the regb_ad arguments cannot cross a DWORD boundary.

imm_data

Data to be written

This argument is reg [31:0].

In both languages, the bits written depend on the length. The following encodes are defined.

  • 4: [31:0]
  • 3: [23:0]
  • 2: [15:0]
  • 1: [7:0]

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