L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
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7.2.1.5. PCI Express Configuration Information Registers

The PCIe Configuration Information duplicate some of the information found in Configuration Space Registers. These registers provide processors residing in the Avalon-MM address domain read access to selected configuration information stored in the PCIe address domain.
Table 68.   PCIe Configuration Information Registers 0x0x3C00–0x3C1F for L-Tile Devices
Address Name Access Description
0x3C00 CONFIG_INFO_0 RO The following fields are defined:
  • [31]: IDO request enable
  • [30]: No snoop enable
  • [29]: Relax order enable
  • [28:24]: Device Number
  • [23:16]: Bus Number
  • [15]: Memory Space Enable
  • [14]: Reserved
  • [13:8]: Auto Negotiation Link Width
  • [ 7]: Bus Master Enable
  • [ 6]: Extended Tag Enable
  • [5:3]: Max Read Request Size
  • [2:0]: Max Payload Size
0x3C04 CONFIG_INFO_1 RO The following fields are defined:
  • [31]: cfg_send_f_err
  • [30]: cfg_send_nf_err
  • [29]: cfg_send_corr_err
  • [28:24] : AER Interrupt Msg No
  • [23:18]: Auto Negotiation Link Width
  • [17]: cfg_pm_no_soft_rs
  • [16]: Read Cpl Boundary (RCB) Control
  • [15:13]: Reserved
  • [12:8]: PCIe Capability Interrupt Msg No
  • [7:5]: Reserved
  • [4]: System Power Control
  • [3:2]: System Attention Indicator Control
  • [1:0]: System Power Indicator Control
0x3C08 CONFIG_INFO_2 RO The following fields are defined:
  • [31]: Reserved
  • [30:24]: Index of Start VF[6:0]
  • [23:16]: Number of VFs
  • [15:12]: Auto Negotiation Link Speed
  • [11:8] ATS STU[4:1]
  • [7]: ATS STU[0]
  • [6]: ATS Cache Enable
  • [5]: ARI forward enable
  • [4]: Atomic request enable
  • [3:2]: TPH ST mode[1:0]
  • [1]: TPH enable[0]
  • [0]: VF enable
0x3C0C CONFIG_INFO_3 RO MSI Address Lower
0x3C10 CONFIG_INFO_4 RO MSI Address Upper
0x3C14 CONFIG_INFO_5 RO MSI Mask
0x3C18 CONFIG_INFO_6 RO The following fields are defined:
  • [31:16] : MSI Data
  • [15:7]: Reserved
  • [6]: MSI-X Func Mask
  • [5]: MSI-X Enable
  • [4:2]: Multiple MSI Enable
  • [ 1]: 64-bit MSI
  • [ 0]: MSI Enable
0x3C1C CONFIG_INFO_7 RO The following fields are defined:
  • [31:10]: Reserved
  • [9:6]: Auto Negotiation Link Speed
  • [5:0]: Auto Negotiation Link Width
Table 69.   PCIe Configuration Information Registers 0x0x3C00–0x3C27 for H-Tile Devices
Address Name Access Description
0x3C00 CONFIG_INFO_0 RO The following fields are defined:
  • [31]: IDO request enable
  • [30]: No snoop enable
  • [29]: Relax order enable
  • [28:24]: Device Number
  • [23:16]: Bus Number
  • [15]: Memory Space Enable
  • [14]: IDO completion enable
  • [13]: perr_en
  • [12]: serr_en
  • [11]: fatal_err_rpt_en
  • [10]: nonfatal_err_rpt_en
  • [9]: corr_err_rpt_en
  • [8]: unsupported_req_rpt_en
  • [ 7]: Bus Master Enable
  • [ 6]: Extended Tag Enable
  • [5:3]: Max Read Request Size
  • [2:0]: Max Payload Size
0x3C04 CONFIG_INFO_1 RO The following fields are defined:
  • [31:16]: Number of VFs [15:0]
  • [15]: pm_no_soft_rst
  • [14]: Read Cpl Boundary (RCB) Control
  • [13]: interrupt disable
  • [12:8]: PCIe Capability Interrupt Msg No
  • [7:5]: Reserved
  • [4]: System Power Control
  • [3:2]: System Attention Indicator Control
  • [1:0]: System Power Indicator Control
0x3C08 CONFIG_INFO_2 RO The following fields are defined:
  • [31:28]: auto negotiation link speed
  • [27:17]: Index of Start VF[10:0]
  • [16:14]: Reserved
  • [13:9]: ATS STU[4:0]
  • [8] ATS cache enable
  • [7]: ARI forward enable
  • [6]: Atomic request enable
  • [5:3]: TPH ST mode
  • [2:1]: TPH enable
  • [0]: VF enable
0x3C0C CONFIG_INFO_3 RO MSI Address Lower
0x3C10 CONFIG_INFO_4 RO MSI Address Upper
0x3C14 CONFIG_INFO_5 RO MSI Mask
0x3C18 CONFIG_INFO_6 RO The following fields are defined:
  • [31:16] : MSI Data
  • [15]: cfg_send_f_err
  • [14]: cfg_send_nf_err
  • [13]: cfg_send_cor_err
  • [12:8]: AER interrupt message number
  • [7]: Reserved
  • [6]: MSI-X func mask
  • [5]: MSI-X enable
  • [4:2]: Multiple MSI enable
  • [ 1]: 64-bit MSI
  • [ 0]: MSI Enable
0x3C1C CONFIG_INFO_7 RO AER uncorrectable error mask
0x3C20 CONFIG_INFO_8 RO AER correctable error mask
0x3C24 CONFIG_INFO_9 RO AER uncorrectable error severity

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