1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Registers 8. Programming Model for the DMA Descriptor Controller 9. Programming Model for the Avalon® -MM Root Port 10. Avalon-MM Testbench and Design Example 11. Troubleshooting and Observing the Link A. PCI Express Core Architecture B. Root Port Enumeration C. Document Revision History
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
7.1.1. Register Access Definitions 7.1.2. PCI Configuration Header Registers 7.1.3. PCI Express Capability Structures 7.1.4. Intel Defined VSEC Capability Header 7.1.5. Uncorrectable Internal Error Status Register 7.1.6. Uncorrectable Internal Error Mask Register 7.1.7. Correctable Internal Error Status Register 7.1.8. Correctable Internal Error Mask Register
184.108.40.206. Avalon-MM to PCI Express Interrupt Status Registers 220.127.116.11. Avalon-MM to PCI Express Interrupt Enable Registers 18.104.22.168. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules 22.214.171.124. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 126.96.36.199. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure 10.5.2. ebfm_barwr_imm Procedure 10.5.3. ebfm_barrd_wait Procedure 10.5.4. ebfm_barrd_nowt Procedure 10.5.5. ebfm_cfgwr_imm_wait Procedure 10.5.6. ebfm_cfgwr_imm_nowt Procedure 10.5.7. ebfm_cfgrd_wait Procedure 10.5.8. ebfm_cfgrd_nowt Procedure 10.5.9. BFM Configuration Procedures 10.5.10. BFM Shared Memory Access Procedures 10.5.11. BFM Log and Message Procedures 10.5.12. Verilog HDL Formatting Functions
The basic Root Port BFM provides a Verilog HDL task‑based interface to test the PCIe* link. The Root Port BFM also handles requests received from the PCIe* link. The following figure provides an overview of the Root Port BFM.
Figure 70. Root Port BFM
The following descriptions provides an overview of the blocks shown in the Root Port BFM figure:
- BFM shared memory (altpcietb_g3bfm_shmem.v): The BFM memory performs the following tasks:
- Stores data received with all completions from the PCI Express link.
- Stores data received with all write transactions received from the PCI Express link.
- Sources data for all completions in response to read transactions received from the PCI Express* link.
- Sources data for most write transactions issued to the link. The only exception is certain BFM PCI Express* write procedures that have a four-byte field of write data passed in the call.
- Stores a data structure that contains the sizes of and the values programmed in the BARs of the Endpoint.
A set of procedures read, write, fill, and check the shared memory from the BFM driver. For details on these procedures, see BFM Shared Memory Access Procedures.
- BFM Read/Write Request Functions (altpcietb_g3bfm_rdwr.v): These functions provide the basic BFM calls for PCI Express* read and write requests. For details on these procedures, refer to BFM Read and Write Procedures.
- BFM Configuration Functions (altpcietb_g3bfm_rp.v ): These functions provide the BFM calls to request configuration of the PCI Express* link and the Endpoint Configuration Space registers. For details on these procedures and functions, refer to BFM Configuration Procedures.
- BFM Log Interface (altpcietb_g3bfm_log.v): The BFM log functions provides routines for writing commonly formatted messages to the simulator standard output and optionally to a log file. It also provides controls that stop simulation on errors. For details on these procedures, refer to BFM Log and Message Procedures.
- BFM Request Interface (altpcietb_g3bfm_req_intf.v): This interface provides the low-level interface between the altpcietb_g3bfm_rdwr.v and altpcietb_g3bfm_configure.v procedures or functions and the Root Port RTL Model. This interface stores a write-protected data structure containing the sizes and the values programmed in the BAR registers of the Endpoint. This interface also stores other critical data used for internal BFM management. You do not need to access these files directly to adapt the testbench to test your Endpoint application.
- Avalon‑ST Interfaces (altpcietb_g3bfm_vc_intf_ast_common.v): These interface modules handle the Root Port interface model. They take requests from the BFM request interface and generate the required PCI Express* transactions. They handle completions received from the PCI Express* link and notify the BFM request interface when requests are complete. Additionally, they handle any requests received from the PCI Express* link, and store or fetch data from the shared memory before generating the required completions.
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