L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.1.1.4. Read Descriptor Table Avalon-MM Slave Interface

This interface is available when you select the internal Descriptor Controller. It receives the Read DMA descriptors which are fetched by the Read Data Mover. Connect the interface to the Read DMA Avalon-MM master interface.

Table 32.  Read Descriptor Table Avalon-MM Slave Interface

Signal Name

Direction

Description

rd_dts_address_i[7:0]

Input

Specifies the descriptor table address.

rd_dts_burst_count_i[4:0]

Input

Specifies the burst count of the transaction in words.

rd_dts_chip_select_i

Input

When asserted, indicates that the read targets this slave interface.

rd_dts_write_data_i[255:0]

Input

Specifies the descriptor.

rd_dts_write_i

Input

When asserted, indicates a write transaction.

rd_dts_wait_request_o

Output When asserted, indicates that the Avalon-MM slave device is not ready to respond.

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