L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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4.1. Avalon-MM Settings

Table 15.  Avalon-MM Settings
Parameter Value Description
Avalon-MM address width

32-bit

64-bit

Specifies the address width for Avalon-MM RX master ports that access Avalon-MM slaves in the Avalon address domain.

When you select Enable Avalon-MM DMA or Enable non-bursting Avalon-MM slave interface with individual byte access (TXS), this value must be set to 64.

Enable Avalon-MM DMA On/Off When On, the IP core includes Read DMA and Write DMA data movers.
Instantiate internal descriptor controller Enabled/Disabled

When On, the descriptor controller is included in the Avalon-MM DMA bridge. When Off, the descriptor controller should be included as a separate external component, if required. The internal descriptor controller does not support Root Port mode.

Enable control register access (CRA) Avalon-MM slave port On/Off

Allows read and write access to Avalon-MM bridge registers from the interconnect fabric using a specialized slave port. This option is required for Requester/Completer variants and optional for Completer Only variants. Enabling this option allows read and write access to Avalon® -MM bridge registers, except in the Completer‑Only single DWORD variations.

Export interrupt conduit interfaces On/Off When On, the IP core exports internal interrupt signals to the top-level RTL module. The exported signals support MSI, MSI-X, and legacy interrupts.
Enable hard IP status bus when using the Avalon-MM interface On/Off When you turn this option On, your top-level variant includes signals that are useful for debugging, including link training and status, and error signals. The following signals are included in the top-level variant:
  • Link status signals
  • ECC error signals
  • LTSSM signals
  • Configuration parity error signal
Enable non-bursting Avalon-MM Slave interface with individual byte access (TXS) On/Off When On, the non-bursting Avalon-MM slave interface is enabled. This interface is appropriate for low bandwidth applications such as accessing control and status registers.
Address width of accessible PCIe memory space (TXS) 22-64 Specifies the number of bits necessary to access the PCIe address space. (This parameter only displays when the TXS slave is enabled.)
Enable high performance bursting Avalon-MM Slave interface (HPTXS) On/Off When On, the high performance Avalon-MM slave interface is enabled. This interface is appropriate for high bandwidth applications such as transferring blocks of data.
Enable mapping (HPTXS) On/Off

Address mapping for 32-bit Avalon-MM slave devices allows system software to specify non-contiguous address pages in the PCI Express address domain. All high performance 32-bit Avalon-MM slave devices are mapped to the 64-bit PCI Express address space. The Avalon-MM Settings tab of the component GUI allows you to select the number and size of address mapping pages.

Up to 10 address mapping pages are supported. The minimum page size is 4 KB. The maximum page size is 4 GB.

When you enable address mapping, the slave address bus width is just large enough to fit the required address mapping pages. When address mapping is disabled, the Avalon-MM slave address bus is set to 64 bits. The Avalon-MM addresses are used as is in the resulting PCIe TLPs.

Address width of accessible PCIe memory space (TXS) 22-64 Specifies the number of bits necessary to access the PCIe address space. (This parameter only displays when the HPTXS slave is enabled.)
Number of address pages (HPTXS) 1-512 pages Specifies the number of pages available for address translation tables. Refer to Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules for more information about address mapping.

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