L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022

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Document Table of Contents

4.2. Base Address Registers

Table 16.  BAR Registers






64-bit prefetchable memory

32-bit non-prefetchable memory

If you select 64-bit prefetchable memory, 2 contiguous BARs are combined to form a 64-bit prefetchable BAR; you must set the higher numbered BAR to Disabled. A non-prefetchable 64‑bit BAR is not supported because in a typical system, the maximum non-prefetchable memory window is 32 bits.

Defining memory as prefetchable allows contiguous data to be fetched ahead. Prefetching memory is advantageous when the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:

  • Reads do not have side effects such as changing the value of the data read
  • Write merging is allowed
Note: BAR0 is not available if the internal descriptor controller is enabled.
Size 0-63

The platform design automatically determines the BAR based on the address width of the slave connected to the master port.

Enable burst capability for Avalon-MM Bar0-5 Master Port On/Off Determines the type of Avalon-MM master to use for this BAR. Two types are available:
  • A high performance, 256-bit master with burst support. This type supports high bandwidth data transfers.
  • A non-bursting 32-bit master with byte level byte enables. This type supports access to control and status registers.
Note: If the Expansion ROM BAR of PF2 or PF3 is disabled, a memory read access to the BAR is responded to with 32'h0000_0000 indicating that the corresponding ROM BAR does not exist. Software should not take any further action to allocate memory space for the disabled ROM BAR. When the Expansion ROM BAR is enabled, the application is required to respond with 16'hAA55 to a memory read to the first two bytes of the ROM space.