L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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4.3. Device Identification Registers

The following table lists the default values of the read-only registers in the PCI* Configuration Header Space. You can use the parameter editor to set the values of these registers. At run time, you can change the values of these registers using the optional Hard IP Reconfiguration block signals.

To access these registers using the Hard IP Reconfiguration interface, make sure that you follow the format of the hip_reconfig_address[20:0] as specified in the table Hard IP Reconfiguration Signals of the section Hard IP Reconfiguration. Use the address offsets specified in the table below for hip_reconfig_address[11:0] and set hip_reconfig_address[20] to 1'b1 for a PCIe space access.

Table 17.   PCI* Header Configuration Space Registers

Register Name

Default Value

Description

Vendor ID

0x00001172

Sets the read-only value of the Vendor ID register. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification.

Address offset: 0x000.

Device ID

0x00000000

Sets the read-only value of the Device ID register.

Address offset: 0x000.

Revision ID

0x00000001

Sets the read-only value of the Revision ID register.

Address offset: 0x008.

Class code

0x00000000

Sets the read-only value of the Class Code register.

Address offset: 0x008.

Subsystem Vendor ID

0x00000000

Sets the read-only value of Subsystem Vendor ID register in the PCI Type 0 Configuration Space. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification. This value is assigned by PCI-SIG to the device manufacturer. This value is only used in Root Port variants.

Address offset: 0x02C.

Subsystem Device ID

0x00000000

Sets the read-only value of the Subsystem Device ID register in the PCI Type 0 Configuration Space. This value is only used in Root Port variants.

Address offset: 0x02C

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