L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

10.1. Avalon-MM Endpoint Testbench

You can generate the testbench from the example design by following the instructions in Quick Start Guide.

Figure 68. Design Example for Endpoint Designs

The Root Port BFM includes the following top-level modules in the <testbench_dir/pcie_<dev>_hip_avmm_bridge_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/DUT_pcie_tb_ip/altera_pcie_s10_tbed_<ver>/sim directory:

  • altpcietb_bfm_top_rp.sv: This is the Root Port PCI Express BFM. For more information about this module, refer to Root Port BFM.
  • altpcietb_bfm_rp_gen3_x8.sv: This module drives transactions to the Root Port BFM. The main process operates in two stages:
    • First, it configures the Endpoint using the task ebfm_cfg_rp_eg.
    • Second, it runs a memory access test with the task target_mem_test or target_mem_test_lite.
    • Finally, it runs a DMA test with the task dma_mem_test.
    This is the module that you modify to vary the transactions sent to the example Endpoint design or your own design.
  • altpcietb_bfm_shmem.v: This memory implements the following functionality:
    • Provides data for TX write operations
    • Provides data for RX read operations
    • Receives data for RX write operations
    • Receives data for received completions

In addition, the testbench has routines that perform the following tasks:

  • Generates the reference clock for the Endpoint at the required frequency.
  • Provides a PCI Express reset at start up.
Note: Before running the testbench, you should set the serial_sim_hwtcl parameter in <testbench_dir>/pcie_ed_tb/ip/pcie_ed_tb/DUT_pcie_tb_ip/sim/DUT_pcie_tb_ip.v. Set to 1 for serial simulation and 0 for PIPE simulation.

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