L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.1.2. Avalon-MM Interface to the Application Layer

This section describes the top-level interfaces available when the Intel L-/H-Tile Avalon-MM for PCI Express IP core does not use the DMA functionality.
Figure 42. Connections: User Application to Avalon-MM DMA Bridge with DMA Descriptor Controller Disabled