1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Registers 8. Programming Model for the DMA Descriptor Controller 9. Programming Model for the Avalon® -MM Root Port 10. Avalon-MM Testbench and Design Example 11. Troubleshooting and Observing the Link A. PCI Express Core Architecture B. Root Port Enumeration C. Document Revision History
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
7.1.1. Register Access Definitions 7.1.2. PCI Configuration Header Registers 7.1.3. PCI Express Capability Structures 7.1.4. Intel Defined VSEC Capability Header 7.1.5. Uncorrectable Internal Error Status Register 7.1.6. Uncorrectable Internal Error Mask Register 7.1.7. Correctable Internal Error Status Register 7.1.8. Correctable Internal Error Mask Register
126.96.36.199. Avalon-MM to PCI Express Interrupt Status Registers 188.8.131.52. Avalon-MM to PCI Express Interrupt Enable Registers 184.108.40.206. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules 220.127.116.11. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 18.104.22.168. PCI Express Configuration Information Registers
10.5.1. ebfm_barwr Procedure 10.5.2. ebfm_barwr_imm Procedure 10.5.3. ebfm_barrd_wait Procedure 10.5.4. ebfm_barrd_nowt Procedure 10.5.5. ebfm_cfgwr_imm_wait Procedure 10.5.6. ebfm_cfgwr_imm_nowt Procedure 10.5.7. ebfm_cfgrd_wait Procedure 10.5.8. ebfm_cfgrd_nowt Procedure 10.5.9. BFM Configuration Procedures 10.5.10. BFM Shared Memory Access Procedures 10.5.11. BFM Log and Message Procedures 10.5.12. Verilog HDL Formatting Functions
New features in the Intel® Quartus® Prime Pro Edition Software:
- Support for Programmer Object File (*.pof) generation for up to Gen3 x8 variants.
- Support for a PCIe* Link Inspector including the following features:
- Read and write access to the Configuration Space registers.
- LTSSM monitoring.
- PLL lock and calibration status monitoring.
- Read and write access to PCS and PMA registers.
- Software application for Linux demonstrating PCIe* accesses in hardware with dynamically generated design examples
- Support for instantiation as a stand-alone IP core from the Intel® Quartus® Prime Pro Edition IP Catalog, as well as Platform Designer instantiation.
The Intel L-/H-Tile Avalon-MM for PCI Express IP Core supports the following features:
- A migration path for Avalon® -MM or Avalon® -MM DMA implemented in earlier device families.
- Standard Avalon® -MM master and slave interfaces:
- High throughput bursting Avalon® -MM slave with optional address mapping.
- Avalon® -MM slave with byte granularity enable support for single DWORD ports and DWORD granularity enable support for high throughput ports.
- Up to 6 Avalon® -MM masters associated to 1 or more BARs with byte enable support.
- High performance, bursting Avalon® -MM master ports.
- Optional DMA data mover with high throughput, bursting, Avalon® -MM master:
- Write Data Mover moves data to PCIe* system memory using PCIe* Memory Write (MemWr) Transaction Layer Packets (TLPs).
- Read Data Mover moves data to local memory using PCIe Memory Read (MemRd) TLPs.
- Modular implementation to select the required features for a specific application:
- Simultaneous support for DMA modules and high throughput Avalon® -MM slaves and masters.
- Avalon® -MM slave to easily access the entire PCIe address space without requiring any PCI Express* specific knowledge.
- Support for 256-bit application interface width.
- Advanced Error Reporting (AER): In Intel® Stratix® 10 devices, Advanced Error Reporting is always enabled in the PCIe Hard IP for both the L and H transceiver tiles.
- Available in both Intel® Quartus® Prime Pro Edition and Platform Designer IP Catalogs.
- Optional internal DMA Descriptor controller.
- Autonomous Hard IP mode, allowing the PCIe IP core to begin operation before the FPGA fabric is programmed. This mode is enabled by default. It cannot be disabled.
Note: Unless Readiness Notifications mechanisms are used (see Section 6.23 of the PCI Express Base Specification), the Root Complex and/or system software must allow at least 1.0 s after a Conventional Reset of a device before it may determine that a device which fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
- Operates at up to 250 MHz in -2 speed grade device.
- The Intel L-/H-Tile Avalon-MM for PCI Express IP supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS).
Note: You cannot change the pin allocations of the Intel L-/H-Tile Avalon-MM for PCI Express IP in the Intel® Quartus® Prime project. However, this IP does support lane reversal and polarity inversion on the PCB by default.
Note: For a detailed understanding of the PCIe* protocol, please refer to the PCI Express* Base Specification.
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