L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022

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Document Table of Contents

1.2. Features

New features in the Intel® Quartus® Prime Pro Edition Software:

  • Support for Programmer Object File (*.pof) generation for up to Gen3 x8 variants.
  • Support for a PCIe* Link Inspector including the following features:
    • Read and write access to the Configuration Space registers.
    • LTSSM monitoring.
    • PLL lock and calibration status monitoring.
    • Read and write access to PCS and PMA registers.
  • Software application for Linux demonstrating PCIe* accesses in hardware with dynamically generated design examples
  • Support for instantiation as a stand-alone IP core from the Intel® Quartus® Prime Pro Edition IP Catalog, as well as Platform Designer instantiation.
The Intel L-/H-Tile Avalon-MM for PCI Express IP Core supports the following features:
  • A migration path for Avalon® -MM or Avalon® -MM DMA implemented in earlier device families.
  • Standard Avalon® -MM master and slave interfaces:
    • High throughput bursting Avalon® -MM slave with optional address mapping.
    • Avalon® -MM slave with byte granularity enable support for single DWORD ports and DWORD granularity enable support for high throughput ports.
    • Up to 6 Avalon® -MM masters associated to 1 or more BARs with byte enable support.
    • High performance, bursting Avalon® -MM master ports.
  • Optional DMA data mover with high throughput, bursting, Avalon® -MM master:
    • Write Data Mover moves data to PCIe* system memory using PCIe* Memory Write (MemWr) Transaction Layer Packets (TLPs).
    • Read Data Mover moves data to local memory using PCIe Memory Read (MemRd) TLPs.
  • Modular implementation to select the required features for a specific application:
    • Simultaneous support for DMA modules and high throughput Avalon® -MM slaves and masters.
    • Avalon® -MM slave to easily access the entire PCIe address space without requiring any PCI Express* specific knowledge.
  • Support for 256-bit application interface width.
  • Advanced Error Reporting (AER): In Intel® Stratix® 10 devices, Advanced Error Reporting is always enabled in the PCIe Hard IP for both the L and H transceiver tiles.
  • Available in both Intel® Quartus® Prime Pro Edition and Platform Designer IP Catalogs.
  • Optional internal DMA Descriptor controller.
  • Autonomous Hard IP mode, allowing the PCIe IP core to begin operation before the FPGA fabric is programmed. This mode is enabled by default. It cannot be disabled.
    Note: Unless Readiness Notifications mechanisms are used (see Section 6.23 of the PCI Express Base Specification), the Root Complex and/or system software must allow at least 1.0 s after a Conventional Reset of a device before it may determine that a device which fails to return a Successful Completion status for a valid Configuration Request is a broken device. This period is independent of how quickly Link training completes.
  • Operates at up to 250 MHz in -2 speed grade device.
  • The Intel L-/H-Tile Avalon-MM for PCI Express IP supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS).
Note: You cannot change the pin allocations of the Intel L-/H-Tile Avalon-MM for PCI Express IP in the Intel® Quartus® Prime project. However, this IP does support lane reversal and polarity inversion on the PCB by default.
Note: For a detailed understanding of the PCIe* protocol, please refer to the PCI Express* Base Specification.