L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.8. Correctable Internal Error Mask Register

Table 62.  Correctable Internal Error Status Register - 0xBBCThe Correctable Internal Error Status register controls which errors are forwarded as Internal Correctable Errors.

Bits

Register Description

Reset Value

Access

[31:12]

Reserved.

0

RO

[11] Mask for correctable ECC error status for Config RAM. 0 RWS
[10] Mask for correctable ECC error status for Retry Buffer. 1 RWS
[9] Mask for correctable ECC error status for Retry Start of TLP RAM. 1 RWS
[8] Reserved. 0 RO
[7] Reserved. 0 RO
[6] Mask for internal Error reported by FPGA. 0 RWS

[5]

Reserved

0

RO

[4]

Mask for PHY Gen3 SKP Error.

1

RWS

[3] Mask for correctable ECC error status for RX Buffer Header RAM #2. 1

RWS

[2] Mask for correctable ECC error status for RX Buffer Header RAM #1. 1

RWS

[1]

Mask for correctable ECC error status for RX Buffer Data RAM #.

1

RWS

[0]

Mask for correctable ECC error status for RX Buffer Data RAM #1.

1

RWS

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