L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.2.3. 32-Bit Control Register Access (CRA) Slave Signals

The CRA interface provides access to the control and status registers of the Avalon-MM bridge. This interface has the following properties:

  • 32-bit data bus
  • Supports a single transaction at a time
  • Supports single-cycle transactions (no bursting)
Note: When the Avalon® -MM Hard IP for PCIe IP Core is in Root Port mode, and the application logic issues a CfgWr or CfgRd via the CRA interface, it needs to fill the Tag field in the TLP Header with the value 0x10 to ensure that the corresponding Completion gets routed to the CRA interface correctly. If the application logic sets the Tag field to some other value, the Avalon® -MM Hard IP for PCIe IP Core does not overwrite that value with the correct value.
Table 41.  Avalon-MM CRA Slave Interface Signals

Signal Name

Direction

Description

cra_read_i

Input

Read enable.

cra_write_i

Input

Write request.

cra_address_i[14:0]

Input

cra_writedata_i[31:0]

Input

Write data. The current version of the CRA slave interface is read-only. Including this signal as part of the Avalon-MM interface, makes future enhancements possible.

cra_readdata[31:0]

Output

Read data lines.

cra_byteenable_i[3:0]

Input

Byte enable.

cra_waitrequest_o

Output

Wait request to hold off additional requests.

cra_chipselect_i

Input

Chip select signal to this slave.

cra_irq_o

Output

Interrupt request. A port request for an Avalon-MM interrupt.

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