L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022
Document Table of Contents

3.4. Clocks and Reset

The Intel L-/H-Tile Avalon-MM for PCI Express generates the Application clock, coreclkout_hip and reset signal. The Avalon-MM bridge provides a synchronized version of the reset signal, app_nreset_status, to the Application. This is an active low reset.

Figure 23.  Intel L-/H-Tile Avalon-MM for PCI Express Clock and Reset Connections
Note: The input reference clock, refclk, must be stable and free-running at device power-up for a successful device configuration.

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