L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.6.1. Serial Data Interface

The IP core supports 1, 2, 4, 8, or 16 lanes.
Table 47.  Serial Data Interface

Signal

Direction

Description

tx_out[<n-1>:0]

Output

Transmit serial data output.
rx_in[<n-1>:0]

Input

Receive serial data input.

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