L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.6. Uncorrectable Internal Error Mask Register

The Uncorrectable Internal Error Mask register controls which errors are forwarded as internal uncorrectable errors.
Table 60.  Uncorrectable Internal Error Mask Register - 0xBB8 The access code RWS stands for Read Write Sticky meaning the value is retained after a soft reset of the IP core.

Bits

Register Description

Reset Value

Access

[31:13]

Reserved.

1b’0

RO

[12] Mask for Debug Bus Interface. 1b'1 RO

[11]

Mask for ECC error from Config RAM block.

1b’1

RWS

[10]

Mask for Uncorrectable ECC error status for Retry Buffer.

1b’1

RO

[9]

Mask for Uncorrectable ECC error status for Retry Start of TLP RAM.

1b’1

RWS

[8]

Mask for RX Transaction Layer parity error reported by IP core.

1b’1

RWS

[7]

Mask for TX Transaction Layer parity error reported by IP core.

1b’1

RWS

[6]

Mask for Uncorrectable Internal error reported by the FPGA.

1b’1

RO

[5]

Reserved.

1b’0

RWS

[4]

Reserved.

1b’1

RWS

[3]

Mask for Uncorrectable ECC error status for RX Buffer Header #2 RAM.

1b’1

RWS

[2]

Mask for Uncorrectable ECC error status for RX Buffer Header #1 RAM.

1b’1

RWS

[1]

Mask for Uncorrectable ECC error status for RX Buffer Data RAM #2.

1b’1

RWS

[0]

Mask for Uncorrectable ECC error status for RX Buffer Data RAM #1.

1b’1

RWS

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