L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

4.4.1. Device Capabilities

Table 18.  Device Registers

Parameter

Possible Values

Default Value

Address

Description

Maximum payload sizes supported

128 bytes

256 bytes

512 bytes

512 bytes

0x074

Specifies the maximum payload size supported. This parameter sets the read-only value of the max payload size supported field of the Device Capabilities register.

A 128-byte read request size results in the lowest latency for typical systems.

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