L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022

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Document Table of Contents

4.4.1. Device Capabilities

Table 18.  Device Registers


Possible Values

Default Value



Maximum payload sizes supported

128 bytes

256 bytes

512 bytes

512 bytes


Specifies the maximum payload size supported. This parameter sets the read-only value of the max payload size supported field of the Device Capabilities register.

A 128-byte read request size results in the lowest latency for typical systems.