L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

10.5.2. ebfm_barwr_imm Procedure

The ebfm_barwr_imm procedure writes up to four bytes of data to an offset from the specified Endpoint BAR.

Location

altpcietb_g3bfm_rdwr.v

Syntax

ebfm_barwr_imm(bar_table, bar_num, pcie_offset, imm_data, byte_len, tclass)

Arguments

bar_table

Address of the Endpoint bar_table structure in BFM shared memory. The bar_table structure stores the address assigned to each BAR so that the driver code does not need to be aware of the actual assigned addresses only the application specific offsets from the BAR.

bar_num

Number of the BAR used with pcie_offset to determine PCI Express address.

pcie_offset

Address offset from the BAR base.

imm_data

Data to be written. In Verilog HDL, this argument is reg [31:0].In both languages, the bits written depend on the length as follows:

Length Bits Written

  • 4: 31 down to 0
  • 3: 23 down to 0
  • 2: 15 down to 0
  • 1: 7 down to 0
byte_len

Length of the data to be written in bytes. Maximum length is 4 bytes.

tclass

Traffic class to be used for the PCI Express transaction.

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