L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683667
Date 11/11/2021
Public
Document Table of Contents

5.4. Channel Layout and PLL Usage

The following figures show the channel layout and PLL usage for Gen1, Gen2 and Gen3, x1, x2, x4, x8 and x16 variants of the Intel L-/H-Tile Avalon-MM for PCI Express IP core. Note that the missing variant Gen3 x16 is supported by another IP core (the Intel L-/H-Tile Avalon-MM+ for PCI Express IP core). For more details on the Avalon® -MM+ IP core, refer to https://www.intel.com/content/www/us/en/programmable/documentation/sox1520633403002.html.

The channel layout is the same for the Avalon® -ST and Avalon® -MM interfaces to the Application Layer.

Note: All of the PCIe hard IP instances in Intel® Stratix® 10 devices are x16. Channels 8-15 are available for other protocols when fewer than 16 channels are used. Refer to Channel Availability for more information.
Figure 26. Gen1 and Gen2 x1
Figure 27. Gen1 and Gen2 x2
Figure 28. Gen1 and Gen2 x4
Figure 29. Gen1 and Gen2 x8
Figure 30. Gen1 and Gen2 x16
Figure 31. Gen3 x1
Figure 32. Gen3 x2
Figure 33. Gen3 x4
Figure 34. Gen3 x8

Did you find the information on this page useful?

Characters remaining:

Feedback Message