L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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9.2. Sending a TLP

The Application Layer performs the following sequence of Avalon® -MM accesses to the CRA slave port to send a TLP Request:
  1. Write the first 32 bits of the TX TLP to RP_TX_REG at address 0x2000.
  2. Set RP_RP_TX_CNTRL[2:0] to 3’b001 to push the first dword of the TLP of the non-posted request into the Root Port TX FIFO.
  3. Write the next 32bits of the TX TLP to RP_TX_REG at address 0x2000.
  4. Set RP_RP_TX_CNTRL[2:0] to 3’b010 if the TPL is completed. Otherwise, set RP_RP_TX_CNTRL[2:0] to 3’b000 to push the next data to the TX FIFO and continue.
  5. Repeat Steps 3 and 4.
  6. When the TLP is completed, the Avalon® -MM bridge will construct the TLP and send it downstream.

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