L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022

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10.3. Avalon® -MM Test Driver Module

The BFM driver module, altpcie_bfm_rp_gen3_x8.sv tests the DMA example Endpoint design. The BFM driver module configures the Endpoint Configuration Space registers and then tests the example Endpoint DMA channel. This file is in the <testbench_dir>pcie_<dev>_hip_avmm_bridge_0_example_design/pcie_example_design_tb/ip/pcie_example_design_tb/DUT_pcie_tb_ip/altera_pcie_<dev>_tbed_<ver>/sim directory.

The BFM test driver module performs the following steps in sequence:

  1. Configures the Root Port and Endpoint Configuration Spaces, which the BFM test driver module does by calling the procedure ebfm_cfg_rp_ep, which is part of altpcietb_bfm_rp_gen3_x8.sv.
  2. Finds a suitable BAR to access the example Endpoint design Control Register space.
  3. If find_mem_baridentifies a suitable BAR in the previous step, the driver performs the following tasks:
    1. DMA read: The driver programs the DMA to read data from the BFM shared memory into the Endpoint memory. The DMA issues an MSI when the last descriptor completes.
    2. DMA writ: The driver programs the DMA to write the data from its Endpoint memory back to the BFM shared memory. The DMA completes the following steps to indicate transfer completion:
      • The DMA issues an MSI when the last descriptor completes.
      • A checker compares the data written back to BFM against the data that read from the BFM.
      • The driver programs the DMA to perform a test that demonstrates downstream access of the DMA Endpoint memory.