L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022

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Document Table of Contents

6. Block Descriptions

The Intel L-/H-Tile Avalon-MM for PCI Express IP core combines the features of the Avalon-MM and Avalon-MM DMA variants of previous generations.The Avalon-MM DMA Bridge includes these functions in soft logic. The DMA bridge is a front-end to the Hard IP for PCI Express IP core. An Avalon-ST scheduler links the DMA bridge and PCIe IP core. It provides round-robin access to TX and RX data streams.
Figure 35.  Intel L-/H-Tile Avalon-MM for PCI Express Block Diagram

You can enable the individual optional modules of the DMA bridge in the component GUI. The following constraints apply:

  • You must enable the PCIe Read DMA module if the PCIe Write DMA module and the Internal DMA Descriptor Controller are enabled. PCIe Read DMA fetches descriptors from the host.
  • You must enable the Control Register Access (CRA) Avalon-MM slave port if address mapping is enabled.
  • When you enable the internal DMA Descriptor Controller, the BAR0 Avalon-MM master is not available. The DMA Descriptor Controller uses this interfaces.