L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

1. Introduction

Updated for:
Intel® Quartus® Prime Design Suite 21.1

This User Guide is applicable to the H-Tile and L-Tile variants of the Intel® Stratix® 10 devices.

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