L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683667
Date 11/11/2021
Public
Document Table of Contents

3.3.1. Avalon-MM Master Interfaces

Avalon-MM Master modules translate PCI Express MRd and MWr TLP requests received from the PCI Express link to Avalon-MM read and write transactions on their Avalon-MM interface. The Avalon-MM master modules return the read data received on their Avalon-MM interface using PCI Express Completion TLPs (CplD).

Up to six Avalon-MM Master interfaces can be enabled at configuration time, one for each of the six supported BARs. Each of the enabled Avalon-MM Master interfaces can be set to be bursting or non-bursting in the component GUI. Bursting Avalon-MM Masters are designed for high throughput transfers, and the application interface data bus width is 256-bit. Non-bursting Avalon-MM Masters are designed for small transfers requiring finer granularity for byte enable control, or for control of 32-bit Avalon-MM Slaves. The prefix for signals comprising this interface is rxm_bar<bar_num>*.

Table 10.  Avalon-MM Master Module Features
Avalon-MM Master Type Data Bus Width Max Burst Size Byte Enable Granularity Maximum Outstanding Read Requests
Non-bursting 32-bit 1 cycle Byte 1
Bursting 256-bit 16 cycles DWord4

32

4 Using less than DWORD granularity has unpredictable results. Buffers must be sized to accommodate DWORD granularity.

Did you find the information on this page useful?

Characters remaining:

Feedback Message