L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Registers 8. Programming Model for the DMA Descriptor Controller 9. Programming Model for the Avalon® -MM Root Port 10. Avalon-MM Testbench and Design Example 11. Troubleshooting and Observing the Link A. PCI Express Core Architecture B. Root Port Enumeration C. Document Revision History
1. Introduction x
1.1. Avalon-MM Interface for PCIe 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Recommended Fabric Speed Grades 1.6. Performance and Resource Utilization 1.7. Transceiver Tiles 1.8. PCI Express IP Core Package Layout 1.9. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
3. Interface Overview x
3.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated 3.2. Avalon-MM DMA Interfaces when Descriptor Controller is Externally Instantiated 3.3. Other Avalon-MM Interfaces 3.4. Clocks and Reset 3.5. System Interfaces
3.3. Other Avalon-MM Interfaces x
3.3.1. Avalon-MM Master Interfaces 3.3.2. Avalon-MM Slave Interfaces 3.3.3. Control Register Access (CRA) Avalon-MM Slave
4. Parameters x
4.1. Avalon-MM Settings 4.2. Base Address Registers 4.3. Device Identification Registers 4.4. PCI Express and PCI Capabilities Parameters 4.5. Configuration, Debug and Extension Options 4.6. PHY Characteristics 4.7. Example Designs
4.4. PCI Express and PCI Capabilities Parameters x
4.4.1. Device Capabilities 4.4.2. Link Capabilities 4.4.3. MSI and MSI-X Capabilities 4.4.4. Slot Capabilities 4.4.5. Power Management 4.4.6. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Channel Layout and PLL Usage
6. Block Descriptions x
6.1. Interfaces
6.1. Interfaces x
6.1.1. Intel® Stratix® 10 DMA Avalon-MM DMA Interface to the Application Layer 6.1.2. Avalon-MM Interface to the Application Layer 6.1.3. Clocks and Reset 6.1.4. Interrupts 6.1.5. Flush Requests 6.1.6. Serial Data, PIPE, Status, Reconfiguration, and Test Interfaces
6.1.1. Intel® Stratix® 10 DMA Avalon-MM DMA Interface to the Application Layer x
6.1.1.1. Descriptor Controller Interfaces when Instantiated Internally 6.1.1.2. Write DMA Avalon-MM Master Port 6.1.1.3. Descriptor Controller Interfaces when Instantiated Externally
6.1.1.1. Descriptor Controller Interfaces when Instantiated Internally x
6.1.1.1.1. Read Data Mover 6.1.1.1.2. Read Descriptor Controller Avalon-MM Master interface 6.1.1.1.3. Write Descriptor Controller Avalon-MM Master Interface 6.1.1.1.4. Read Descriptor Table Avalon-MM Slave Interface 6.1.1.1.5. Write Descriptor Table Avalon-MM Slave Interface
6.1.1.3. Descriptor Controller Interfaces when Instantiated Externally x
6.1.1.3.1. Avalon® -ST Descriptor Source
6.1.2. Avalon-MM Interface to the Application Layer x
6.1.2.1. Bursting and Non-Bursting Avalon® -MM Module Signals 6.1.2.2. Non-Bursing Slave Module 6.1.2.3. 32-Bit Control Register Access (CRA) Slave Signals 6.1.2.4. Bursting Slave Module
6.1.3. Clocks and Reset x
6.1.3.1. Clocks 6.1.3.2. Resets
6.1.4. Interrupts x
6.1.4.1. MSI Interrupts for Endpoints 6.1.4.2. Legacy Interrupts
6.1.6. Serial Data, PIPE, Status, Reconfiguration, and Test Interfaces x
6.1.6.1. Serial Data Interface 6.1.6.2. PIPE Interface 6.1.6.3. Hard IP Status Interface 6.1.6.4. Hard IP Reconfiguration 6.1.6.5. Test Interface
7. Registers x
7.1. Configuration Space Registers 7.2. Avalon-MM DMA Bridge Registers
7.1. Configuration Space Registers x
7.1.1. Register Access Definitions 7.1.2. PCI Configuration Header Registers 7.1.3. PCI Express Capability Structures 7.1.4. Intel Defined VSEC Capability Header 7.1.5. Uncorrectable Internal Error Status Register 7.1.6. Uncorrectable Internal Error Mask Register 7.1.7. Correctable Internal Error Status Register 7.1.8. Correctable Internal Error Mask Register
7.1.4. Intel Defined VSEC Capability Header x
7.1.4.1. Intel Defined Vendor Specific Header 7.1.4.2. Intel Marker 7.1.4.3. JTAG Silicon ID 7.1.4.4. User Configurable Device and Board ID
7.2. Avalon-MM DMA Bridge Registers x
7.2.1. PCI Express Avalon-MM Bridge Register Address Map 7.2.2. DMA Descriptor Controller Registers
7.2.1. PCI Express Avalon-MM Bridge Register Address Map x
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers 7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules 7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 7.2.1.5. PCI Express Configuration Information Registers
7.2.2. DMA Descriptor Controller Registers x
7.2.2.1. Read DMA Internal Descriptor Controller Registers 7.2.2.2. Write DMA Internal Descriptor Controller Registers
8. Programming Model for the DMA Descriptor Controller x
8.1. Read DMA Example 8.2. Write DMA Example 8.3. Software Program for Simultaneous Read and Write DMA 8.4. Read DMA and Write DMA Descriptor Format
9. Programming Model for the Avalon® -MM Root Port x
9.1. Root Port TLP Data Control and Status Registers 9.2. Sending a TLP 9.3. Receiving a Non-Posted Completion TLP 9.4. Example of Reading and Writing BAR0 Using the CRA Interface
10. Avalon-MM Testbench and Design Example x
10.1. Avalon-MM Endpoint Testbench 10.2. Endpoint Design Example 10.3. Avalon® -MM Test Driver Module 10.4. Root Port BFM 10.5. BFM Procedures and Functions
10.2. Endpoint Design Example x
10.2.1. BAR Setup
10.4. Root Port BFM x
10.4.1. Overview 10.4.2. Issuing Read and Write Transactions to the Application Layer 10.4.3. Configuration of Root Port and Endpoint 10.4.4. Configuration Space Bus and Device Numbering 10.4.5. BFM Memory Map
10.5. BFM Procedures and Functions x
10.5.1. ebfm_barwr Procedure 10.5.2. ebfm_barwr_imm Procedure 10.5.3. ebfm_barrd_wait Procedure 10.5.4. ebfm_barrd_nowt Procedure 10.5.5. ebfm_cfgwr_imm_wait Procedure 10.5.6. ebfm_cfgwr_imm_nowt Procedure 10.5.7. ebfm_cfgrd_wait Procedure 10.5.8. ebfm_cfgrd_nowt Procedure 10.5.9. BFM Configuration Procedures 10.5.10. BFM Shared Memory Access Procedures 10.5.11. BFM Log and Message Procedures 10.5.12. Verilog HDL Formatting Functions
10.5.9. BFM Configuration Procedures x
10.5.9.1. ebfm_cfg_rp_ep Procedure 10.5.9.2. ebfm_cfg_decode_bar Procedure
10.5.10. BFM Shared Memory Access Procedures x
10.5.10.1. Shared Memory Constants 10.5.10.2. shmem_write Task 10.5.10.3. shmem_read Function 10.5.10.4. shmem_display Verilog HDL Function 10.5.10.5. shmem_fill Procedure 10.5.10.6. shmem_chk_ok Function
10.5.11. BFM Log and Message Procedures x
10.5.11.1. ebfm_display Verilog HDL Function 10.5.11.2. ebfm_log_stop_sim Verilog HDL Function 10.5.11.3. ebfm_log_set_suppressed_msg_mask Task 10.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 10.5.11.5. ebfm_log_open Verilog HDL Function 10.5.11.6. ebfm_log_close Verilog HDL Function
10.5.12. Verilog HDL Formatting Functions x
10.5.12.1. himage1 10.5.12.2. himage2 10.5.12.3. himage4 10.5.12.4. himage8 10.5.12.5. himage16 10.5.12.6. dimage1 10.5.12.7. dimage2 10.5.12.8. dimage3 10.5.12.9. dimage4 10.5.12.10. dimage5 10.5.12.11. dimage6 10.5.12.12. dimage7
11. Troubleshooting and Observing the Link x
11.1. Troubleshooting 11.2. PCIe Link Inspector Overview
11.1. Troubleshooting x
11.1.1. Simulation Fails To Progress Beyond Polling.Active State 11.1.2. Hardware Bring-Up Issues 11.1.3. Link Training 11.1.4. Use Third-Party PCIe Analyzer
11.2. PCIe Link Inspector Overview x
11.2.1. PCIe* Link Inspector Hardware
11.2.1. PCIe* Link Inspector Hardware x
11.2.1.1. Enabling the PCIe* Link Inspector 11.2.1.2. Launching the PCIe* Link Inspector 11.2.1.3. The PCIe* Link Inspector LTSSM Monitor 11.2.1.4. Accessing the Configuration Space and Transceiver Registers 11.2.1.5. Additional Status Commands
11.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
11.2.1.3.1. LTSSM Monitor Registers 11.2.1.3.2. ltssm_save2file <file_name> 11.2.1.3.3. ltssm_file2console 11.2.1.3.4. ltssm_debug_check 11.2.1.3.5. ltssm_display <num_states> 11.2.1.3.6. ltssm_save_oldstates
11.2.1.4. Accessing the Configuration Space and Transceiver Registers x
11.2.1.4.1. PCIe* Link Inspector Commands 11.2.1.4.2. NPDME PLL and Channel Commands 11.2.1.4.3. Register Address Map
11.2.1.5. Additional Status Commands x
11.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
A. PCI Express Core Architecture x
A.1. Transaction Layer A.2. Data Link Layer A.3. Physical Layer
C. Document Revision History x
C.1. Document Revision History for the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Troubleshooting and Observing the Link
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Document Revision History

7.1. Configuration Space Registers

Table 51.  Correspondence between Configuration Space Capability Structures and the PCIe Base Specification Description

Byte Address

Configuration Space Register

Corresponding Section in PCIe Specification

0x000-0x03C

PCI Header Type 0 Configuration Registers

Type 0 Configuration Space Header

0x040-0x04C

Power Management

 PCI Power Management Capability Structure

0x050-0x05C

MSI Capability Structure

MSI Capability Structure, see also and PCI Local Bus Specification

0x060-0x06C Reserved N/A

0x070-0x0A8

PCI Express Capability Structure

PCI Express Capability Structure

0x0B0-0x0B8

MSI-X Capability Structure

MSI-X Capability Structure, see also and PCI Local Bus Specification

0x0BC-0x0FC Reserved N/A
0x100-0x134 Advanced Error Reporting (AER) (for PFs only) Advanced Error Reporting Capability
0x138-0x184 Reserved N/A

0x188-0x1B0

Secondary PCI Express Extended Capability Header

PCI Express Extended Capability

0x1B4

 Reserved

N/A
0x1B8-0x1F4 SR-IOV Capability Structure SR-IOV Extended Capability Header in Single Root I/O Virtualization and Sharing Specification, Rev, 1.1
0x1F8-0x1D0 Transaction Processing Hints (TPH) Requester Capability TLP Processing Hints (TPH)
0x1D4-0x280 Reserved N/A
0x284-0x288 Address Translation Services (ATS) Capability Structure Address Translation Services Extended Capability (ATS) in Single Root I/O Virtualization and Sharing Specification, Rev. 1.1

0xB80-0xBFC

Intel-Specific

Vendor-Specific Header (Header only)

0xC00

Optional Custom Extensions

N/A
0xC00 Optional Custom Extensions N/A
Table 52.  Summary of Configuration Space Register Fields

Byte Address

Hard IP Configuration Space Register

Corresponding Section in PCIe Specification

0x000

Device ID, Vendor ID

Type 0 Configuration Space Header

0x004

Status, Command

Type 0 Configuration Space Header

0x008

Class Code, Revision ID

Type 0 Configuration Space Header

0x00C

Header Type, Cache Line Size

Type 0 Configuration Space Header

0x010

Base Address 0

Base Address Registers

0x014

Base Address 1

Base Address Registers

0x018

Base Address 2

Base Address Registers

0x01C

Base Address 3

Base Address Registers

0x020

Base Address 4

Base Address Registers

0x024

Base Address 5

Base Address Registers

0x028

Reserved

N/A

0x02C

Subsystem ID, Subsystem Vendor ID

Type 0 Configuration Space Header

0x030

Reserved

N/A

0x034

Capabilities Pointer

Type 0 Configuration Space Header

0x038

Reserved

N/A

0x03C

Interrupt Pin, Interrupt Line

Type 0 Configuration Space Header

0x040 PME_Support, D1, D2, etc. PCI Power Management Capability Structure
0x044 PME_en, PME_Status, etc. Power Management Status and Control Register

0x050

MSI-Message Control, Next Cap Ptr, Capability ID

MSI and MSI-X Capability Structures

0x054

Message Address

MSI and MSI-X Capability Structures

0x058

Message Upper Address

MSI and MSI-X Capability Structures

0x05C

Reserved Message Data

MSI and MSI-X Capability Structures

0x0B0

MSI-X Message Control Next Cap Ptr Capability ID

MSI and MSI-X Capability Structures

0x0B4

MSI-X Table Offset BIR

MSI and MSI-X Capability Structures

0x0B8

Pending Bit Array (PBA) Offset BIR

MSI and MSI-X Capability Structures

0x100

PCI Express Enhanced Capability Header

Advanced Error Reporting Enhanced Capability Header

0x104

Uncorrectable Error Status Register

Uncorrectable Error Status Register

0x108

Uncorrectable Error Mask Register

Uncorrectable Error Mask Register

0x10C

Uncorrectable Error Mask Register

Uncorrectable Error Severity Register

0x110

Correctable Error Status Register

Correctable Error Status Register

0x114

Correctable Error Mask Register

Correctable Error Mask Register

0x118

Advanced Error Capabilities and Control Register

Advanced Error Capabilities and Control Register

0x11C

Header Log Register

Header Log Register

0x12C

Root Error Command

Root Error Command Register

0x130

Root Error Status

Root Error Status Register

0x134

Error Source Identification Register Correctable Error Source ID Register

Error Source Identification Register

0x188

Next Capability Offset, PCI Express Extended Capability ID

Secondary PCI Express Extended Capability

0x18C

Enable SKP OS, Link Equalization Req, Perform Equalization

Link Control 3 Register
0x190

Lane Error Status Register

Lane Error Status Register

0x194:0x1B0

Lane Equalization Control Register

Lane Equalization Control Register
0xB80 VSEC Capability Header Vendor-Specific Extended Capability Header
0xB84 VSEC Length, Revision, ID Vendor-Specific Header
0xB88 Intel Marker Intel-Specific Registers
0xB8C JTAG Silicon ID DW0
0xB90 JTAG Silicon ID DW1
0xB94 JTAG Silicon ID DW2
0xB98 JTAG Silicon ID DW3
0xB9C User Device and Board Type ID
0xBA0:0xBAC Reserved
0xBB0 General Purpose Control and Status Register
0xBB4 Uncorrectable Internal Error Status Register
0xBB8 Uncorrectable Internal Error Mask Register
0xBBC Correctable Error Status Register
0xBC0 Correctable Error Mask Register
0xBC4:BD8 Reserved N/A
0xC00 Optional Custom Extensions N/A

Section Content
Register Access Definitions
PCI Configuration Header Registers
PCI Express Capability Structures
Intel Defined VSEC Capability Header
Uncorrectable Internal Error Status Register
Uncorrectable Internal Error Mask Register
Correctable Internal Error Status Register
Correctable Internal Error Mask Register

Related Information
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