L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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11.2. PCIe Link Inspector Overview

Use the PCIe* Link Inspector to monitor the PCIe* link at the Physical, Data Link and Transaction Layers.

The following figure provides an overview of the debug capability available when you enable all of the options on the Configuration, Debug and Extension Option tab of the Intel L-/H-Tile Avalon-ST for PCI Express IP component GUI.

Figure 75. Overview of PCIe* Link Inspector Hardware

As this figure illustrates, the PCIe* Link (pli*) commands provide access to the following registers:

  • The PCI Express* Configuration Space registers
  • LTSSM monitor registers
  • ATX PLL dynamic partial reconfiguration I/O (DPRIO) registers from the dynamic reconfiguration interface
  • fPLL DPRIO registers from the dynamic reconfiguration interface
  • Native PHY DPRIO registers from the dynamic reconfiguration interface

The NPDME commands (currently called adme*_) provide access to the following registers

  • ATX PLL DPRIO registers from the ATX PLL NPDME interface
  • fPLL DPRIO registers from the fPLL NPDME interface
  • Native PHY DPRIO registers from the Native PHY NPDME interface

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