L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022

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Document Table of Contents Bursting and Non-Bursting Avalon® -MM Module Signals

The Avalon® -MM Master module translates read and write TLPs received from the PCIe* link to Avalon® -MM transactions for connected slaves. You can enable up to six Avalon® -MM Master interfaces. One of the six Base Address Registers (BARs) define the base address for each master interface. This module allows other PCIe* components, including host software, to access the Avalon® -MM slaves connected in the Platform Designer.

The Enable burst capability for Avalon-MM Bar0-5 Master Port parameter on the Base address register tab determines the type of Avalon® -MM master to use for each BAR. Two types are available:

  • A high performance, 256-bit master with burst support. This type supports high bandwidth data transfers.
  • A non-bursting 32-bit master with byte level byte enables. This type supports for access to control and status registers.
Table 39.  Avalon-MM RX Master Interface Signals <n> = the BAR number, and can be 0, 1, 2, 3, 4, or 5.

Signal Name





Asserted by the core to request a write to an Avalon-MM slave.



The address of the Avalon-MM slave being accessed.



RX data being written to slave



Dword enables for write data.


(available in burst mode only)


The burst count, measured in 256-bit words of the RX write or read request. The maximum data in a burst is 512 bytes. This optional signal is available only when you turn on Enable burst capability for RXM Avalon-MM BAR<n> Master ports.



Asserted by the external Avalon-MM slave to hold data transfer.



Asserted by the core to request a read.



Read data returned from Avalon-MM slave in response to a read request. This data is sent to the IP core through the TX interface.



Asserted by the system interconnect fabric to indicate that the read data is valid.

rxm_irq_i[<m>:0], <m> < 16


Connect interrupts to the Avalon® -MM interface. These signals are only available for the Avalon® -MM when the CRA port is enabled. A rising edge triggers an MSI interrupt. The hard IP core converts this event to an MSI interrupt and sends it to the Root Port. The host reads the Interrupt Status register to retrieve the interrupt vector. Host software services the interrupt and notifies the target upon completion.

As many as 16 individual interrupt signals (<m>≤15) are available. If rxm_irq_<n>[<m>:0] is asserted on consecutive cycles without the deassertion of all interrupt inputs, no MSI message is sent for subsequent interrupts. To avoid losing interrupts, software must ensure that all interrupt sources are cleared for each MSI message received.
Note: These signals are not available when the IP core is operating in DMA mode (i.e. when the Enable Avalon-MM DMA option in the Avalon-MM Settings tab of the GUI is set to On).

The following timing diagram illustrates the RX master port propagating requests to the Application Layer and also shows simultaneous read and write activities.

Figure 43. Simultaneous RXM Read and RXM Write
Figure 44. RX Master Interface