L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.5. Flush Requests

In the PCI Express* protocol, a memory read request from the host with a length of 1 dword and byte enables being all 0’s translate to a flush request for the Completer, which in this case is the Intel L-/H-Tile Avalon-MM for PCI Express IP core. However, this flush request feature is not supported by the IP core.

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