L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.4.4. User Configurable Device and Board ID

Table 58.  User Configurable Device and Board ID - 0xB9C

Bits

Register Description

Default Value

Access

[15:0]

Allows you to specify ID of the .sof file to be loaded.

From configuration bits RO

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