L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

1.7. Transceiver Tiles

Intel® Stratix® 10 introduces several transceiver tile variants to support a wide variety of protocols.
Figure 2.  Intel® Stratix® 10 Transceiver Tile Block Diagram
Table 6.  Transceiver Tiles Channel Types
Tile Device Type Channel Capability Channel Hard IP Access
Chip-to-Chip Backplane
L-Tile GX 26 Gbps (NRZ) 12.5 Gbps (NRZ) PCIe Gen3x16
H-Tile GX 28.3 Gbps (NRZ) 28.3 Gbps (NRZ) PCIe Gen3x16
E-Tile GXE

30 Gbps (NRZ),

56 Gbps (PAM-4)

30 Gbps (NRZ),

56 Gbps (PAM-4)

100G Ethernet

L-Tile and H-Tile

Both L and H transceiver tiles contain four transceiver banks-with a total of 24 duplex channels, eight ATX PLLs, eight fPLLs, eight CMU PLLs, a PCIe Hard IP block, and associated input reference and transmitter clock networks. L and H transceiver tiles also include 10GBASE-KR/40GBASE-KR4 FEC block in each channel.

L-Tiles have transceiver channels that support up to 26 Gbps chip-to-chip or 12.5 Gbps backplane applications. H-Tiles have transceiver channels to support 28 Gbps applications. H-Tile channels support fast lock-time for Gigabit-capable passive optical network (GPON).

Intel® Stratix® 10 GX/SX devices incorporate L-Tiles or H-Tiles. Package migration is available with Intel® Stratix® 10 GX/SX from L-Tile to H-Tile variants.

E-Tile

E-Tiles are designed to support 56 Gbps with PAM-4 signaling or up to 30 Gbps backplane with NRZ signaling. E-Tiles do not include any PCIe* Hard IP blocks.

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