L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
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11.2.1.3.1. LTSSM Monitor Registers

You can program the LTSSM monitor registers to change the default behavior.

Table 79.  LTSSM Registers

Base Address

LTSSM Address Access

Description

0x20000 7 0x00 RW

LTSSM Monitor Control register. The LTSSM Monitor Control includes the following fields:

  • [1:0]: Timer Resolution Control. Specifies the number of hip_reconfig_clk the PCIe* link remains in each LTSSM state. The following encodings are defined:
    • 2’b00: The main timer increments each hip_reconfig_clk cycle. This is the default value.
    • 2’b01: The main timer increments each 16 hip_reconfig_clk cycles.
    • 2’b10: The main timer increments each 256 hip_reconfig_clk cycles.
    • 2’b11: The main timer increments each <n> hip_reconfig_clk cycles. The Timer Resolution Step field defines <n>.

  • [17:2]: Timer Resolution Step. Specifies the value of <n> when Timer Resolution Control = 2'b11.
  • [18]: LTSSM FIFO reset. The following encodings are defined:
    • 1'b0: The LTSSM FIFO operates normally.
    • 1'b1: The LTSSM FIFO is in reset.
  • [19]: Reserved.
  • [20]: LTSSM State Match Enable. The following encodings are defined:
    • 1’b0: The LTSSM State match function is disabled
    • 1'b1: The LTSSM State match function is enabled.When the current LTSSM state matches a state stored in the LTSSM State Match register, the State Match Flag asserts.
  • [27:22] LTSSM State Match. When enabled, the LTSSM monitor compares the value in this register against each LTSSM state. If the values match, the LTSSM state match flag (offset address 0x01, bit 29) is set to 1.

  • [31:28]: Reserved.
0x01 RO

LTSSM Quick Debug Status register. The LTSSM Quick Debug Status register includes the following fields:

  • [9:0]: Number LTSSM States. Specifies the number of states currently stored in the FIFO.
  • [10]: LTSSM FIFO Full Flag. When asserted, the LTSSM FIFO is full.
  • [11]: LTSSM FIFO Empty Flag. When asserted, the LTSSM FIFO is empty.
  • [12]: Current PERSTN Status. Stores the current PERSTN value.
  • [13]: Current SERDES PLL Locked. The following encodings are defined:
    • 1'b0: The SERDES PLL is not locked.
    • 1'b1: The SERDES PLL is locked.
  • [14]: PCIe* Link Status. The following encodings are defined:
    • 1'b0: The link is down.
    • 1'b1: The link is up.
  • [16:15] Current PCIe* Data Rate. The following encodings are defined:
    • 2'b00: Reserved.
    • 2’b01=Gen1.
    • 2’b10=Gen2.
    • 2’b11=Gen3.
  • [17]: Native PHY Channel Locked to Data. The following encodings are defined:
    • 1'b0: At least one CDR channel is not locked to data.
    • 1'b1: All CDR channels are locked to data.
  • [21:18]: Current Number of PCIe* Active Lanes.
  • [22]: Reserved.
  • [28:23]: Current LTSSM State.
  • [29]: LTSSM State Match Flag. Asserts when the current state matches the state you specify in LTSSM State Match.
  • [31:30]: Reserved.
0x02 RO

LTSSM FIFO Output.

Reading this register is equivalent to reading one entry from the LTSSM FIFO. Reading this register also updates the LTSSM FIFO, 0x03. The following fields are defined:
  • [5:0] LTSSM State.
  • [7:6]: PCIe Current Speed.

  • [12:8:] PCIe Lane Act.

  • [13]: SerDes PLL Locked.

  • [14]: Link Up.

  • [15]: PERSTN.

  • [16]:Native PHY Channel 0. When asserted, the CDR is locked to data.

  • [17]: Native PHY Channel 1. When asserted, the CDR is locked to data.

  • [18]: Native PHY Channel 2. When asserted, the CDR is locked to data.

  • [19]: Native PHY Channel 3. When asserted, the CDR is locked to data.

  • [20]: Native PHY Channel 4. When asserted, the CDR is locked to data.
  • [21]: Native PHY Channel 5. When asserted, the CDR is locked to data.
  • [22]: Native PHY Channel 6. When asserted, the CDR is locked to data.
  • [23]: Native PHY Channel 7. When asserted, the CDR is locked to data.
  • [24]: Native PHY Channel 8. When asserted, the CDR is locked to data.

  • [25]: Native PHY Channel 9. When asserted, the CDR is locked to data.

  • [26]: Native PHY Channel 10. When asserted, the CDR is locked to data.

  • [27]: Native PHY Channel 11. When asserted, the CDR is locked to data.

  • [29]: Native PHY Channel 12. When asserted, the CDR is locked to data.

  • [28]: Native PHY Channel 13. When asserted, the CDR is locked to data.

  • [30]: Native PHY Channel 14. When asserted, the CDR is locked to data.

  • [31]: Native PHY Channel 15. When asserted, the CDR is locked to data.

0x03 RO

LTSSM FIFO Output [63:32]

[29:0] Main Timer. The timer resets to 0 on each LTSSM transition. The value in this register indicates how long the PCIe* link remains in each LTSSM state.

0x04 RW

LTSSM Skip State Storage Control register. Use this register to specify a maximum of 4 LTSSM states. When LTSSM State Skip Enable is on, the LTSSM FIFO does not store the specified state or states.

Refer to LTSSM State Encodings for the LTSSM Skip Field for the state encodings.

[5:0]: LTSSM State 1.

[6]: LTSSM State 1 Skip Enable.

[12:7]: LTSSM State 2.

[13]: LTSSM State 2 Skip Enable.

[19:14]: LTSSM State 3.

[20]: LTSSM State 3 Skip Enable.

[26:21]: LTSSM State 4.

[27]: LTSSM State 4 Skip Enable.

Table 80.  LTSSM State Encodings for the LTSSM Skip Field
State Encoding
Detect.Quiet 6'h00
Detect.Active 6'h01
Polling.Active 6'h02
Polling.Compliance 6'h03
Polling.Configuration 6'h04
PreDetect.Quiet 6'h05
Detect.Wait 6'h06
Configuration.Linkwidth.Start 6'h07
Configuration.Linkwidth.Accept 6'h08
Configuration.Lanenum.Wait 6'h09
Configuration.Lanenum.Accept 6'h0A
Configuration.Complete 6'h0B
Configuration.Idle 6'h0C
Recovery.RcvrLock 6'h0D
Recovery.Speed 6'h0E
Recovery.RcvrCfg 6'h0F
Recovery.Idle 6'h10
Recovery.Equalization Phase 0 6'h20
Recovery.Equalization Phase 1 6'h21
Recovery.Equalization Phase 2 6'h22
Recovery.Equalization Phase 3 6'h23
L0 6'h11
L0s 6'h12
L123.SendEIdle 6'h13
L1.Idle 6'h14
L2.Idle 6'h15
L2.TransmitWake 6'h16
Disabled.Entry 6'h17
Disabled.Idle 6'h18
Disabled 6'h19
Loopback.Entry 6'h1A
Loopback.Active 6'h1B
Loopback.Exit 6'h1C
Loopback.Exit.Timeout 6'h1D
HotReset.Entry 6'h1E
Hot.Reset 6'h1F
7 When the Enable PCIe Link Inspector AVMM Interface option is On, the base address of the LTSSM Registers becomes 0x8000. Use this value to access these registers via the pli_avmm_master_address[19:0] ports.

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