L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Quick Start Guide 3. Interface Overview 4. Parameters 5. Designing with the IP Core 6. Block Descriptions 7. Registers 8. Programming Model for the DMA Descriptor Controller 9. Programming Model for the Avalon® -MM Root Port 10. Avalon-MM Testbench and Design Example 11. Troubleshooting and Observing the Link A. PCI Express Core Architecture B. Root Port Enumeration C. Document Revision History
1. Introduction x
1.1. Avalon-MM Interface for PCIe 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Recommended Fabric Speed Grades 1.6. Performance and Resource Utilization 1.7. Transceiver Tiles 1.8. PCI Express IP Core Package Layout 1.9. Channel Availability
2. Quick Start Guide x
2.1. Design Components 2.2. Hardware and Software Requirements 2.3. Directory Structure 2.4. Generating the Design Example 2.5. Simulating the Design Example 2.6. Compiling the Design Example and Programming the Device 2.7. Installing the Linux Kernel Driver 2.8. Running the Design Example Application
3. Interface Overview x
3.1. Avalon-MM DMA Interfaces when Descriptor Controller Is Internally Instantiated 3.2. Avalon-MM DMA Interfaces when Descriptor Controller is Externally Instantiated 3.3. Other Avalon-MM Interfaces 3.4. Clocks and Reset 3.5. System Interfaces
3.3. Other Avalon-MM Interfaces x
3.3.1. Avalon-MM Master Interfaces 3.3.2. Avalon-MM Slave Interfaces 3.3.3. Control Register Access (CRA) Avalon-MM Slave
4. Parameters x
4.1. Avalon-MM Settings 4.2. Base Address Registers 4.3. Device Identification Registers 4.4. PCI Express and PCI Capabilities Parameters 4.5. Configuration, Debug and Extension Options 4.6. PHY Characteristics 4.7. Example Designs
4.4. PCI Express and PCI Capabilities Parameters x
4.4.1. Device Capabilities 4.4.2. Link Capabilities 4.4.3. MSI and MSI-X Capabilities 4.4.4. Slot Capabilities 4.4.5. Power Management 4.4.6. Vendor Specific Extended Capability (VSEC)
5. Designing with the IP Core x
5.1. Generation 5.2. Simulation 5.3. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition) 5.4. Channel Layout and PLL Usage
6. Block Descriptions x
6.1. Interfaces
6.1. Interfaces x
6.1.1. Intel® Stratix® 10 DMA Avalon-MM DMA Interface to the Application Layer 6.1.2. Avalon-MM Interface to the Application Layer 6.1.3. Clocks and Reset 6.1.4. Interrupts 6.1.5. Flush Requests 6.1.6. Serial Data, PIPE, Status, Reconfiguration, and Test Interfaces
6.1.1. Intel® Stratix® 10 DMA Avalon-MM DMA Interface to the Application Layer x
6.1.1.1. Descriptor Controller Interfaces when Instantiated Internally 6.1.1.2. Write DMA Avalon-MM Master Port 6.1.1.3. Descriptor Controller Interfaces when Instantiated Externally
6.1.1.1. Descriptor Controller Interfaces when Instantiated Internally x
6.1.1.1.1. Read Data Mover 6.1.1.1.2. Read Descriptor Controller Avalon-MM Master interface 6.1.1.1.3. Write Descriptor Controller Avalon-MM Master Interface 6.1.1.1.4. Read Descriptor Table Avalon-MM Slave Interface 6.1.1.1.5. Write Descriptor Table Avalon-MM Slave Interface
6.1.1.3. Descriptor Controller Interfaces when Instantiated Externally x
6.1.1.3.1. Avalon® -ST Descriptor Source
6.1.2. Avalon-MM Interface to the Application Layer x
6.1.2.1. Bursting and Non-Bursting Avalon® -MM Module Signals 6.1.2.2. Non-Bursing Slave Module 6.1.2.3. 32-Bit Control Register Access (CRA) Slave Signals 6.1.2.4. Bursting Slave Module
6.1.3. Clocks and Reset x
6.1.3.1. Clocks 6.1.3.2. Resets
6.1.4. Interrupts x
6.1.4.1. MSI Interrupts for Endpoints 6.1.4.2. Legacy Interrupts
6.1.6. Serial Data, PIPE, Status, Reconfiguration, and Test Interfaces x
6.1.6.1. Serial Data Interface 6.1.6.2. PIPE Interface 6.1.6.3. Hard IP Status Interface 6.1.6.4. Hard IP Reconfiguration 6.1.6.5. Test Interface
7. Registers x
7.1. Configuration Space Registers 7.2. Avalon-MM DMA Bridge Registers
7.1. Configuration Space Registers x
7.1.1. Register Access Definitions 7.1.2. PCI Configuration Header Registers 7.1.3. PCI Express Capability Structures 7.1.4. Intel Defined VSEC Capability Header 7.1.5. Uncorrectable Internal Error Status Register 7.1.6. Uncorrectable Internal Error Mask Register 7.1.7. Correctable Internal Error Status Register 7.1.8. Correctable Internal Error Mask Register
7.1.4. Intel Defined VSEC Capability Header x
7.1.4.1. Intel Defined Vendor Specific Header 7.1.4.2. Intel Marker 7.1.4.3. JTAG Silicon ID 7.1.4.4. User Configurable Device and Board ID
7.2. Avalon-MM DMA Bridge Registers x
7.2.1. PCI Express Avalon-MM Bridge Register Address Map 7.2.2. DMA Descriptor Controller Registers
7.2.1. PCI Express Avalon-MM Bridge Register Address Map x
7.2.1.1. Avalon-MM to PCI Express Interrupt Status Registers 7.2.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 7.2.1.3. Address Mapping for High-Performance Avalon-MM 32-Bit Slave Modules 7.2.1.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 7.2.1.5. PCI Express Configuration Information Registers
7.2.2. DMA Descriptor Controller Registers x
7.2.2.1. Read DMA Internal Descriptor Controller Registers 7.2.2.2. Write DMA Internal Descriptor Controller Registers
8. Programming Model for the DMA Descriptor Controller x
8.1. Read DMA Example 8.2. Write DMA Example 8.3. Software Program for Simultaneous Read and Write DMA 8.4. Read DMA and Write DMA Descriptor Format
9. Programming Model for the Avalon® -MM Root Port x
9.1. Root Port TLP Data Control and Status Registers 9.2. Sending a TLP 9.3. Receiving a Non-Posted Completion TLP 9.4. Example of Reading and Writing BAR0 Using the CRA Interface
10. Avalon-MM Testbench and Design Example x
10.1. Avalon-MM Endpoint Testbench 10.2. Endpoint Design Example 10.3. Avalon® -MM Test Driver Module 10.4. Root Port BFM 10.5. BFM Procedures and Functions
10.2. Endpoint Design Example x
10.2.1. BAR Setup
10.4. Root Port BFM x
10.4.1. Overview 10.4.2. Issuing Read and Write Transactions to the Application Layer 10.4.3. Configuration of Root Port and Endpoint 10.4.4. Configuration Space Bus and Device Numbering 10.4.5. BFM Memory Map
10.5. BFM Procedures and Functions x
10.5.1. ebfm_barwr Procedure 10.5.2. ebfm_barwr_imm Procedure 10.5.3. ebfm_barrd_wait Procedure 10.5.4. ebfm_barrd_nowt Procedure 10.5.5. ebfm_cfgwr_imm_wait Procedure 10.5.6. ebfm_cfgwr_imm_nowt Procedure 10.5.7. ebfm_cfgrd_wait Procedure 10.5.8. ebfm_cfgrd_nowt Procedure 10.5.9. BFM Configuration Procedures 10.5.10. BFM Shared Memory Access Procedures 10.5.11. BFM Log and Message Procedures 10.5.12. Verilog HDL Formatting Functions
10.5.9. BFM Configuration Procedures x
10.5.9.1. ebfm_cfg_rp_ep Procedure 10.5.9.2. ebfm_cfg_decode_bar Procedure
10.5.10. BFM Shared Memory Access Procedures x
10.5.10.1. Shared Memory Constants 10.5.10.2. shmem_write Task 10.5.10.3. shmem_read Function 10.5.10.4. shmem_display Verilog HDL Function 10.5.10.5. shmem_fill Procedure 10.5.10.6. shmem_chk_ok Function
10.5.11. BFM Log and Message Procedures x
10.5.11.1. ebfm_display Verilog HDL Function 10.5.11.2. ebfm_log_stop_sim Verilog HDL Function 10.5.11.3. ebfm_log_set_suppressed_msg_mask Task 10.5.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 10.5.11.5. ebfm_log_open Verilog HDL Function 10.5.11.6. ebfm_log_close Verilog HDL Function
10.5.12. Verilog HDL Formatting Functions x
10.5.12.1. himage1 10.5.12.2. himage2 10.5.12.3. himage4 10.5.12.4. himage8 10.5.12.5. himage16 10.5.12.6. dimage1 10.5.12.7. dimage2 10.5.12.8. dimage3 10.5.12.9. dimage4 10.5.12.10. dimage5 10.5.12.11. dimage6 10.5.12.12. dimage7
11. Troubleshooting and Observing the Link x
11.1. Troubleshooting 11.2. PCIe Link Inspector Overview
11.1. Troubleshooting x
11.1.1. Simulation Fails To Progress Beyond Polling.Active State 11.1.2. Hardware Bring-Up Issues 11.1.3. Link Training 11.1.4. Use Third-Party PCIe Analyzer
11.2. PCIe Link Inspector Overview x
11.2.1. PCIe* Link Inspector Hardware
11.2.1. PCIe* Link Inspector Hardware x
11.2.1.1. Enabling the PCIe* Link Inspector 11.2.1.2. Launching the PCIe* Link Inspector 11.2.1.3. The PCIe* Link Inspector LTSSM Monitor 11.2.1.4. Accessing the Configuration Space and Transceiver Registers 11.2.1.5. Additional Status Commands
11.2.1.3. The PCIe* Link Inspector LTSSM Monitor x
11.2.1.3.1. LTSSM Monitor Registers 11.2.1.3.2. ltssm_save2file <file_name> 11.2.1.3.3. ltssm_file2console 11.2.1.3.4. ltssm_debug_check 11.2.1.3.5. ltssm_display <num_states> 11.2.1.3.6. ltssm_save_oldstates
11.2.1.4. Accessing the Configuration Space and Transceiver Registers x
11.2.1.4.1. PCIe* Link Inspector Commands 11.2.1.4.2. NPDME PLL and Channel Commands 11.2.1.4.3. Register Address Map
11.2.1.5. Additional Status Commands x
11.2.1.5.1. Displaying PLL Lock and Calibration Status Registers
A. PCI Express Core Architecture x
A.1. Transaction Layer A.2. Data Link Layer A.3. Physical Layer
C. Document Revision History x
C.1. Document Revision History for the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide
1. Introduction
2. Quick Start Guide
3. Interface Overview
4. Parameters
5. Designing with the IP Core
6. Block Descriptions
7. Registers
8. Programming Model for the DMA Descriptor Controller
9. Programming Model for the Avalon® -MM Root Port
10. Avalon-MM Testbench and Design Example
11. Troubleshooting and Observing the Link
A. PCI Express Core Architecture
B. Root Port Enumeration
C. Document Revision History

11.2.1.3.1. LTSSM Monitor Registers

You can program the LTSSM monitor registers to change the default behavior.

Table 79.  LTSSM Registers

Base Address

 LTSSM Address Access

Description

0x20000 7 0x00 RW

LTSSM Monitor Control register. The LTSSM Monitor Control includes the following fields:

  • [1:0]: Timer Resolution Control. Specifies the number of hip_reconfig_clk the PCIe* link remains in each LTSSM state. The following encodings are defined:
    • 2’b00: The main timer increments each hip_reconfig_clk cycle. This is the default value.
    • 2’b01: The main timer increments each 16 hip_reconfig_clk cycles.
    • 2’b10: The main timer increments each 256 hip_reconfig_clk cycles.

    • 2’b11: The main timer increments each <n> hip_reconfig_clk cycles. The Timer Resolution Step field defines <n>.

  • [17:2]: Timer Resolution Step. Specifies the value of <n> when Timer Resolution Control = 2'b11.
  • [18]: LTSSM FIFO reset. The following encodings are defined:
    • 1'b0: The LTSSM FIFO operates normally.
    • 1'b1: The LTSSM FIFO is in reset.
  • [19]: Reserved.
  • [20]: LTSSM State Match Enable. The following encodings are defined:
    • 1’b0: The LTSSM State match function is disabled
    • 1'b1: The LTSSM State match function is enabled.When the current LTSSM state matches a state stored in the LTSSM State Match register, the State Match Flag asserts.

  • [27:22] LTSSM State Match. When enabled, the LTSSM monitor compares the value in this register against each LTSSM state. If the values match, the LTSSM state match flag (offset address 0x01, bit 29) is set to 1.

  • [31:28]: Reserved.
0x01 RO

LTSSM Quick Debug Status register. The LTSSM Quick Debug Status register includes the following fields:

  • [9:0]: Number LTSSM States. Specifies the number of states currently stored in the FIFO.
  • [10]: LTSSM FIFO Full Flag. When asserted, the LTSSM FIFO is full.
  • [11]: LTSSM FIFO Empty Flag. When asserted, the LTSSM FIFO is empty.
  • [12]: Current PERSTN Status. Stores the current PERSTN value.
  • [13]: Current SERDES PLL Locked. The following encodings are defined:
    • 1'b0: The SERDES PLL is not locked.
    • 1'b1: The SERDES PLL is locked.
  • [14]: PCIe* Link Status. The following encodings are defined:
    • 1'b0: The link is down.
    • 1'b1: The link is up.
  • [16:15] Current PCIe* Data Rate. The following encodings are defined:
    • 2'b00: Reserved.
    • 2’b01=Gen1.
    • 2’b10=Gen2.
    • 2’b11=Gen3.
  • [17]: Native PHY Channel Locked to Data. The following encodings are defined:
    • 1'b0: At least one CDR channel is not locked to data.
    • 1'b1: All CDR channels are locked to data.
  • [21:18]: Current Number of PCIe* Active Lanes.
  • [22]: Reserved.
  • [28:23]: Current LTSSM State.
  • [29]: LTSSM State Match Flag. Asserts when the current state matches the state you specify in LTSSM State Match.
  • [31:30]: Reserved.
0x02 RO

LTSSM FIFO Output.

Reading this register is equivalent to reading one entry from the LTSSM FIFO. Reading this register also updates the LTSSM FIFO, 0x03. The following fields are defined:
  • [5:0] LTSSM State.

  • [7:6]: PCIe Current Speed.

  • [12:8:] PCIe Lane Act.

  • [13]: SerDes PLL Locked.

  • [14]: Link Up.

  • [15]: PERSTN.

  • [16]:Native PHY Channel 0. When asserted, the CDR is locked to data.

  • [17]: Native PHY Channel 1. When asserted, the CDR is locked to data.

  • [18]: Native PHY Channel 2. When asserted, the CDR is locked to data.

  • [19]: Native PHY Channel 3. When asserted, the CDR is locked to data.

  • [20]: Native PHY Channel 4. When asserted, the CDR is locked to data.
  • [21]: Native PHY Channel 5. When asserted, the CDR is locked to data.
  • [22]: Native PHY Channel 6. When asserted, the CDR is locked to data.
  • [23]: Native PHY Channel 7. When asserted, the CDR is locked to data.

  • [24]: Native PHY Channel 8. When asserted, the CDR is locked to data.

  • [25]: Native PHY Channel 9. When asserted, the CDR is locked to data.

  • [26]: Native PHY Channel 10. When asserted, the CDR is locked to data.

  • [27]: Native PHY Channel 11. When asserted, the CDR is locked to data.

  • [29]: Native PHY Channel 12. When asserted, the CDR is locked to data.

  • [28]: Native PHY Channel 13. When asserted, the CDR is locked to data.

  • [30]: Native PHY Channel 14. When asserted, the CDR is locked to data.

  • [31]: Native PHY Channel 15. When asserted, the CDR is locked to data.

0x03 RO

LTSSM FIFO Output [63:32]

[29:0] Main Timer. The timer resets to 0 on each LTSSM transition. The value in this register indicates how long the PCIe* link remains in each LTSSM state.

0x04 RW

LTSSM Skip State Storage Control register. Use this register to specify a maximum of 4 LTSSM states. When LTSSM State Skip Enable is on, the LTSSM FIFO does not store the specified state or states.

Refer to LTSSM State Encodings for the LTSSM Skip Field for the state encodings.

[5:0]: LTSSM State 1.

[6]: LTSSM State 1 Skip Enable.

[12:7]: LTSSM State 2.

[13]: LTSSM State 2 Skip Enable.

[19:14]: LTSSM State 3.

[20]: LTSSM State 3 Skip Enable.

[26:21]: LTSSM State 4.

[27]: LTSSM State 4 Skip Enable.

Table 80.  LTSSM State Encodings for the LTSSM Skip Field
State Encoding
Detect.Quiet 6'h00
Detect.Active 6'h01
Polling.Active 6'h02
Polling.Compliance 6'h03
Polling.Configuration 6'h04
PreDetect.Quiet 6'h05
Detect.Wait 6'h06
Configuration.Linkwidth.Start 6'h07
Configuration.Linkwidth.Accept 6'h08
Configuration.Lanenum.Wait 6'h09
Configuration.Lanenum.Accept 6'h0A
Configuration.Complete 6'h0B
Configuration.Idle 6'h0C
Recovery.RcvrLock 6'h0D
Recovery.Speed 6'h0E
Recovery.RcvrCfg 6'h0F
Recovery.Idle 6'h10
Recovery.Equalization Phase 0 6'h20
Recovery.Equalization Phase 1 6'h21
Recovery.Equalization Phase 2 6'h22
Recovery.Equalization Phase 3 6'h23
L0 6'h11
L0s 6'h12
L123.SendEIdle 6'h13
L1.Idle 6'h14
L2.Idle 6'h15
L2.TransmitWake 6'h16
Disabled.Entry 6'h17
Disabled.Idle 6'h18
Disabled 6'h19
Loopback.Entry 6'h1A
Loopback.Active 6'h1B
Loopback.Exit 6'h1C
Loopback.Exit.Timeout 6'h1D
HotReset.Entry 6'h1E
Hot.Reset 6'h1F
7 When the Enable PCIe Link Inspector AVMM Interface option is On, the base address of the LTSSM Registers becomes 0x8000. Use this value to access these registers via the pli_avmm_master_address[19:0] ports.
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