L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

11.2.1.4.1. PCIe* Link Inspector Commands

These commands use the PCIe* Link Inspector connection to read and write registers in the Configuration Space, LTSSM monitor, PLLs, and Native PHY channels.

Table 81.   PCIe* Link Inspector (PLI) Commands These commands are available in the link_insp_test_suite.tcl script.
Command Description
pli_read32 <slave_if> <pli_base_addr> <pli_reg_addr> Performs a 32-bit read from the slave interface at the base address and register address specified.
pli_read8 <slave_if> <base_addr> <reg_addr> Performs an 8-bit read from the slave interface at the base address and register address specified.
pli_write32 <slave_if> <pli_base_addr> <pli_reg_addr> <value> Performs a 32-bit write of the value specified to the slave interface at the base address and the register address specified.
pli_write8 <slave_if> <base_addr> <reg_addr> <value> Performs an 8-bit write of the value specified to the slave interface at the base address and the register address specified.
pli_rmw32 <slave_if> <base_addr> <reg_addr> <bit_mask> <value> Performs a 32-bit read-modify-write of the value specified to the slave interface to the slave interface at the base address and register address using the bit mask specified.
pli_rmw8 <slave_if> <base_addr> <reg_addr> <bit_mask> <value> Performs an 8-bit read-modify-write to the slave interface at the base address and register address using the bit mask specified.
pli_dump_to_file <slave_if> <filename> <base_addr> <start_reg_addr> <end_reg_addr>

Writes the contents of the slave interface to the file specified. The base address and the start and end register addresses specify range of the write.

The <slave_if> argument can have the following values:

  • $atxpll
  • $fpll
  • $channel(<n>)

PCIe* Link Inspector Command Examples

The following commands use the addresses specified below in the Register Address Map.

Use the following command to read register 0x480 from the ATX PLL:

% pli_read8 $pli_adme $atxpll_base_addr 0x480

Use the following command to write 0xFF to the fPLL register at address 0x4E0:

% pli_write8 $pli_adme $fpll_base_addr 0x4E0 0xFF

Use the following command to perform a read-modify-write to write 0x02 to channel 3 with a bit mask of 0x03 for the write:

% pli_rmw8 $pli_adme $xcvr_ch3_base_addr 0x481 0x03 0x02

Use the following command to instruct the LTSSM monitor to skip recording of the Recovery.Rcvlock state:

$pli_write $pli_adme $ltssm_base_addr 0x04 0x0000000D 

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