L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.1.1.5. Write Descriptor Table Avalon-MM Slave Interface

This interface is available when you select the internal Descriptor Controller. This interface receives the Write DMA descriptors which are fetched by Read Data Mover. Connect the interface to the Read DMA Avalon-MM master interface.

Table 33.  Write Descriptor Table Avalon-MM Slave Interface

Signal Name

Direction

Description

wr_dts_address_i[7:0]

Input

Specifies the descriptor table address.

wr_dts_burst_count_i[4:0] or [5:0]

Input

Specifies the burst count of the transaction in words.

wr_dts_chip_select_i

Input

When asserted, indicates that the write is for this slave interface.

wr_dts_wait_request_o

Output

When asserted, indicates that this interface is busy and is not ready to respond.

wr_dts_write_data_i[255:0]

Input

Drives the descriptor table entry data.

wr_dts_write_i

Input

When asserted, indicates a write transaction.

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