L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: nik1410905453404
Ixiasoft
Visible to Intel only — GUID: nik1410905453404
Ixiasoft
6.1.1.1. Descriptor Controller Interfaces when Instantiated Internally
The Descriptor Controller includes two, 128-entry FIFOs to store the read and write descriptor tables. The Descriptor Controller forwards the descriptors to the Read DMA and Write DMA Data Movers.
The Data Movers send completion status to the Read Descriptor Controller and Write Descriptor Controller. The Descriptor Controller forwards status and MSI to the host using the TX slave port.