L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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11.2.1. PCIe* Link Inspector Hardware

When you enable, the PCIe* Link Inspector, the altera_pcie_s10_hip_ast_pipen1b module of the generated IP includes the PCIe* Link Inspector as shown in the figure below.

Figure 76.  Intel L-/H-Tile Avalon-ST for PCI Express IP with the PCIe* Link Inspector

You drive the PCIe* Link Inspector from a System Console running on a separate test PC. The System Console connects to the PCIe* Link Inspector via a Native PHY Debug Master Endpoint (NPDME). An Intel® FPGA Download Cable makes this connection.

You can also access low-level link status information from the PCIe Hard IP, XCVR or PLL blocks via the Link Inspector Avalon® -MM Interface by enabling the Enable PCIe Link Inspector Avalon® -MM Interface option in the IP GUI. See the section Enabling the Link Inspector for more details. When you enable this option, you do not need to use the System Console. The pli_avmm_* ports that are exposed connect directly to the LTSSM Monitor without going through an NPDME block.

Figure 77.  Intel L-/H-Tile Avalon-ST for PCI Express IP with the PCIe* Link Inspector and the Link Inspector Avalon® -MM Interface Enabled
Note:

To use the PCIe* Link Inspector, enable the Hard IP dynamic reconfiguration and Transceiver dynamic reconfiguration along with the Link Inspector itself. As a result, the IP exports four clocks (hip_reconfig_clk, xcvr_reconfig_clk, reconfig_pll0_clk and reconfig_pll1_clk) and four resets (hip_reconfig_rst_n, xcvr_reconfig_reset, reconfig_pll0_reset and reconfig_pll1_reset) to the IP block symbol. These signals provide the clocks and resets to the following interfaces:

  • The NPDME module
  • FPLL reconfiguration interface (reconfig_pll0)
  • ATXPLL reconfiguration interface (reconfig_pll1)
  • Transceiver reconfiguration interface (xcvr_reconfig)
  • Hard IP reconfiguration interface (hip_reconfig)

When you run a dynamically-generated design example on the Intel® Stratix® 10-GX Development Kit, these signals are automatically connected.

If you run the PCIe* Link Inspector on your own hardware, be sure to connect the four clocks mentioned above to a clock source of up to 100 MHz. Additionally, ensure that the four resets mentioned above are connected to an appropriate reset signal.

When you generate a PCIe* design example (with a PCIe* IP instantiated) without enabling the Link Inspector, the following interfaces are not exposed at the top level of the PCIe* IP:

  • FPLL reconfiguration interface (reconfig_pll0)
  • ATXPLL reconfiguration interface (reconfig_pll1)
  • Transceiver reconfiguration interface (xcvr_reconfig)
  • Hard IP reconfiguration interface (hip_reconfig)

If you later want to enable the Link Inspector using the same design, you need to provide a free-running clock and a reset to drive these interfaces at the top level of the PCIe* IP. Intel recommends that you generate a new design example with the Link Inspector enabled. When you do so, the design example will include a free-running clock and a reset for all reconfiguration interfaces.

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