L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
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6.1.6.3. Hard IP Status Interface

Hard IP Status: This optional interface includes the following signals that are useful for debugging, including: link status signals, interrupt status signals, TX and RX parity error signals, correctable and uncorrectable error signals.
Table 49.  Hard IP Status Interface

Signal

Direction

Description

derr_cor_ext_rcv

Output

When asserted, indicates that the RX buffer detected a 1-bit (correctable) ECC error. This is a pulse stretched output.
derr_cor_ext_rpl

Output

When asserted, indicates that the retry buffer detected a 1-bit (correctable) ECC error. This is a pulse stretched output.
derr_rpl

Output

When asserted, indicates that the retry buffer detected a 2-bit (uncorrectable) ECC error. This is a pulse stretched output.
derr_uncor_ext_rcv

Output

When asserted, indicates that the RX buffer detected a 2-bit (uncorrectable) ECC error. This is a pulse stretched output.

int_status[10:0](H-Tile)

int_status[7:0] (L-Tile)

int_status_pf1[7:0] (L-Tile)

Output

The int_status[3:0] signals drive legacy interrupts to the application (for H-Tile).

The int_status[10:4] signals provide status for other interrupts (for H-Tile).

The int_status[3:0] signals drive legacy interrupts to the application for PF0 (for L-Tile).

The int_status[7:4] signals provide status for other interrupts for PF0 (for L-Tile).

The int_status_pf1[3:0] signals drive legacy interrupts to the application for PF1 (for L-Tile).

The int_status_pf1[7:4] signals provide status for other interrupts for PF1 (for L-Tile).

The following signals are defined:

  • int_status[0]: Interrupt signal A
  • int_status[1]: Interrupt signal B
  • int_status[2]: Interrupt signal C
  • int_status[3]: Interrupt signal D
  • int_status[4]: Specifies a Root Port AER error interrupt. This bit is set when the cfg_aer_rc_err_msi or cfg_aer_rc_err_int signal asserts. This bit is cleared when software writes 1 to the register bit or when cfg_aer_rc_err_int is deasserts.
  • int_status[5]: Specifies the Root Port PME interrupt status. It is set when cfg_pme_msi or cfg_pme_int asserts. It is cleared when software writes a 1 to clear or when cfg_pme_int deasserts.
  • int_status[6]: Asserted when a hot plug event occurs and Power Management Events (PME) are enabled. (PMEs are typically used to revive the system or a function from a low power state.)
  • int_status[7]: Specifies the hot plug event interrupt status.
  • int_status[8]: Specifies the interrupt status for the Link Autonomous Bandwidth Status register. H-Tile only.
  • int_status[9]: Specifies the interrupt status for the Link Bandwidth Management Status register. H-Tile only.
  • int_status[10]: Specifies the interrupt status for the Link Equalization Request bit in the Link Status register. H-Tile only.
int_status_common[2:0]

Output

Specifies the interrupt status for the following registers. When asserted, indicates that an interrupt is pending:

  • int_status_common[0]: Autonomous bandwidth status register.
  • int_status_common[1]: Bandwidth management status register.
  • int_status_common[2]: Link equalization request bit in the link status register.
lane_act[4:0]

Output

Lane Active Mode: This signal indicates the number of lanes that configured during link training. The following encodings are defined:

  • 5’b0 0001: 1 lane
  • 5’b0 0010: 2 lanes
  • 5’b0 0100: 4 lanes
  • 5’b0 1000: 8 lanes
  • 5'b1 0000: 16 lanes
link_up

Output

When asserted, the link is up.
ltssmstate[5:0]

Output

Link Training and Status State Machine (LTSSM) state: The LTSSM state machine encoding defines the following states:

  • 6'h00 - Detect.Quiet
  • 6'h01 - Detect.Active
  • 6'h02 - Polling.Active
  • 6'h03 - Polling.Compliance
  • 6'h04 - Polling.Configuration
  • 6'h05 - PreDetect.Quiet
  • 6'h06 - Detect.Wait
  • 6'h07 - Configuration.Linkwidth.Start
  • 6'h08 - Configuration.Linkwidth.Accept
  • 6'h09 - Configuration.Lanenum.Wait
  • 6'h0A - Configuration.Lanenum.Accept
  • 6'h0B - Configuration.Complete
  • 6'h0C - Configuration.Idle
  • 6'h0D - Recovery.RcvrLock
  • 6'h0E - Recovery.Speed
  • 6'h0F - Recovery.RcvrCfg
  • 6'h10 - Recovery.Idle
  • 6'h20 - Recovery.Equalization Phase 0
  • 6'h21 - Recovery.Equalization Phase 1
  • 6'h22 - Recovery.Equalization Phase 2
  • 6'h23 - Recovery.Equalization Phase 3
  • 6'h11 - L0
  • 6'h12 - L0s
  • 6'h13 - L123.SendEIdle
  • 6'h14 - L1.Idle
  • 6'h15 - L2.Idle
  • 6'h16 - L2.TransmitWake
  • 6'h17 - Disabled.Entry
  • 6'h18 - Disabled.Idle
  • 6'h19 - Disabled
  • 6'h1A - Loopback.Entry
  • 6'h1B - Loopback.Active
  • 6'h1C - Loopback.Exit
  • 6'h1D - Loopback.Exit.Timeout
  • 6'h1E - HotReset.Entry
  • 6'h1F - Hot.Reset
rx_par_err

Output

Asserted for a single cycle to indicate that a parity error was detected in a TLP at the input of the RX buffer. This error is logged as an uncorrectable internal error in the VSEC registers. For more information, refer to Uncorrectable Internal Error Status Register. If this error occurs, you must reset the Hard IP because parity errors can leave the Hard IP in an unknown state.
tx_par_err

Output

Asserted for a single cycle to indicate a parity error during TX TLP transmission. The IP core transmits TX TLP packets even when a parity error is detected.

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