L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

C.1. Document Revision History for the L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Document Version Intel® Quartus® Prime Version Changes
2021.11.11 21.1 Removed references to the 64-bit Application interface data width from all chapters since only the 256-bit interface width is supported.
2021.10.19 21.1 Changed the device support level for Intel® Stratix® 10 to Final Support in the Device Family Support section.
2021.05.27 21.1

Added an Appendix chapter on Root Port enumeration.

Added a note to the Features section stating that L- and H-tile Avalon® Memory-mapped IP for PCI Express only supports the Separate Reference Clock With No Spread Spectrum architecture (SRNS), but not the Separate Reference Clock With Independent Spread Spectrum architecture (SRIS).

2021.04.12 20.3 Added a note to the Features and Generating the Design Example sections stating that pin allocations for this IP cannot be changed in the Intel® Quartus® Prime project, but the IP does support lane reversal and polarity inversion on the PCB by default.
2020.10.05 20.3

Updated the IP name to Intel L-/H-tile Avalon Memory-mapped IP for PCI Express.

Removed the Simple DMA design example option from the Generating the Design Example section as that design example is no longer available.

Added a note to the Read Data Mover section stating that Completion TLPs are restricted to a data payload of up to 256 bytes.

2020.06.03 20.1 Added the description for the new input ninit_done to the Resets section under Clocks and Resets. Also added a link to AN 891: Using the Reset Release Intel FPGA IP, which describes the Reset Release IP that is used to drive the ninit_done input.
2020.05.11 20.1 Changed the Altera Debug Master Endpoint (ADME) to Native PHY Debug Master Endpoint (NPDME).
2020.04.23 19.3 Updated the ready latency value in section Avalon® -ST Descriptor Source from 3 cycles to 1 cycle.
2020.04.22 19.3

Updated the document title to Intel® Stratix® 10 H-Tile and L-Tile Avalon® memory mapped Hard IP for PCI Express* User Guide to meet new legal naming guidelines.

Fixed a typo in the byte address of some Reserved bits in Table 51. Correspondence between Configuration Space Capability Structures and the PCIe Base Specification Description.

2020.03.25 19.3

Added notes stating that the Hard IP Reconfiguration interface is not accessible if the PCIe Link Inspector is enabled to the System Interfaces and Hard IP Reconfiguration Interface sections.

2020.01.03 19.3

Updated resource utilization numbers for the Gen1 x1 variant.

Added notes stating that the Gen3 x16 variant is supported by the Intel® Stratix® 10 Avalon® Memory Mapped (Avalon-MM) Hard IP+ for PCI Express* .

2019.09.30 19.3

Added a note to clarify that this User Guide is applicable to H-Tile and L-Tile variants of the Intel® Stratix® 10 devices only.

Added Autonomous Hard IP mode to the Features section.

2019.07.18 19.1 Added a note stating that refclk must be stable and free-running at device power-up for a successful device configuration.
2019.03.30 19.1

Added a chapter on the programming model for Root Ports.

Removed the note stating that Root Port mode is not recommended.

Removed the BIOS Enumeration section from the Troubleshooting chapter.

2019.03.12 18.1.1 Updated the E-Tile PAM-4 frequency to 57.8G and NRZ frequency to 28.9G.
2019.03.04 18.1.1 Updated the commands to run VCS, NCSim and Xcelium simulations in the Simulating the Design Example topic.
2018.12.24 18.1.1

Added the description for the Link Inspector Avalon® -MM Interface.

Added the Avalon® -MM-to-PCIe rxm_irq for MSI feature.

2018.10.26 18.1 Added the statements that the IP core does not support the L1/L2 low-power states, the in-band beacon and sideband WAKE# signal.
2018.09.24 18.1

Added the ltssm_file2console and ltssm_save_oldstates commands for the PCIe* Link Inspector.

Updated the steps to run ModelSim simulations for a design example.

Updated the steps to run a design example.

2018.08.29 18.0 Added the step to invoke vsim to the instructions for running a ModelSim simulation.
Date Version Changes
May 2018 18.0

Made the following changes to the user guide:

  • Edited the chapter on 32-Bit Control Register Access (CRA) to state that in RP mode, application logic must set the Tag field in the TLP Header to 0x10.
  • Added the note that AER is always enabled to the Features chapter.
  • Added a sub-topic in the chapter Interfaces to state that flush requests are not supported.
  • Updated the chapter PCI Express Configuration Information Registers to state that Extended Tag is not supported.
  • Updated the GUI screenshot and the list of steps in Generating the Design Example. Also added a description for the recommended_pinassignments_s10.txt file.
  • Updated the chapter Parameters to add the Application Interface Width parameter and the configurations available when the 64-bit option for that parameter is chosen.
  • Updated the chapters Interface Overview, Avalon-MM Master Interfaces, and Avalon-MM Slave Interfaces to state that DMA operations are available for 256-bit application interface width but not for 64-bit, and add a row for the 64-bit bursting case to the features table.
November 2017 17.1 Removed Enable RX-polarity inversion in soft logic parameter. This parameter is not required for Intel® Stratix® 10 devices.
November 2017 17.1

Made the following changes to the user guide:

  • Revised the Testbench and Design Example for the Avalon-MM Interface chapter. Although the functions and tasks that implement the testbench have not changed, the organization of these functions and task in files is entirely different than in earlier device families.
  • Improved descriptions of the DMA registers.
  • Revised Generating the Avalon® -MM Design to generate the example design from the .ip file. This IP core is now available in the Intel® Quartus® Prime Pro Edition IP Catalog.
  • Added definition for rxm_irq_<n>[15:0]. This signal is available for the Avalon® -MM interface when you enable the CRA port.
  • Added bit encoding for the Expansion ROM which is supported in this release.
  • Corrected address range for Lane Equalization Control Register in the Correspondence between Configuration Space Capability Structures and PCIe Base Specification Correspondence between Configuration Space Capability Structures and PCIe* Base Specification Description table. Up to 16 lanes each have a 4-byte register.
  • Corrected the Legacy Interrupt Assertion and Legacy Interrupt Deassertion figures. Intel® Stratix® 10 devices do not support the app_int_ack signal.
  • Updated maximum throughput for L-Tile transceivers from 17.4 Gbps to 26 Gbps.
  • Removed -3 from the recommended speed grades.
  • Added note that you must treat BAR0 as non-prefetchable when you enable the internal Descriptor Controller.
  • Removed description of testin_zero. This signal is not a top-level signal of the IP.

Made the following changes to the Intel® Stratix® 10 hard IP for PCI Express* IP core:

  • This IP core is now available in the Intel® Quartus® Prime Pro Edition IP Catalog.
May 2017 Quartus®Prime Pro v17.1 Stratix 10 ES Editions Software

Made the following changes to the IP core:

  • Added (*.pof) support for up to Gen3 x8 variants with an .ini file.
  • Added support for the H-Tile transceiver.
  • Added support for a Gen3x16 simulation model that you can use in an Avery testbench.

Made the following changes to the user guide:

  • Added descriptions for DMA Descriptor Controller registers.
  • Replaced the Getting Started with the Avalon-MM DMA static design example with the dynamically generated Quick Start Guide design example.
  • Added Performance and Resource Utilization results.
  • Changed Read DMA Example to use larger data block transfers.
  • Added Write DMA Example.
  • Added Testbench and Design Example for the Avalon-MM Interface chapter.
  • Added reference to AN-811: Using the Avery BFM for PCI Express Gen3x16 Simulation on Intel Stratix 10 Devices.
  • Added figures showing the connections between the Avalon-MM DMA bridge and user application and between the PCIe IP core system interfaces and user application.
  • Revised Generation discussion to match the Quartus® Prime Pro – Stratix 10 Edition 17.1 Interim Release design flow.
  • Added definitions for Advance, Preliminary, and Final timing models.
  • Fixed minor errors and typos.
October 2016 Quartus® Prime Pro – Stratix 10 Edition Beta

Initial release

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