L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

11.2.1.5.1. Displaying PLL Lock and Calibration Status Registers

  1. Run the following System Console Tcl commands to display the lock and the calibration status for the PLLs and channels.

    % source TCL/setup_adme.tcl

    % source TCL/xcvr_pll_suite.tcl

  2. Here are sample transcripts:
    ##########################################
    #####         ATXPLL  Status         #####
    ##########################################
    ATXPLL is Locked
    ATXPLL Calibration is Done
    ##########################################
    #####          FPLL  Status          #####
    ##########################################
    FPLL is Locked
    FPLL Calibration is Done
    ##########################################
    #####       Channel# 0 Status        #####
    ##########################################
    Channel#0 CDR is Locked to Data
    Channel#0 CDR is Locked to Reference Clock
    Channel#0 TX Calibration is Done
    Channel#0 RX Calibration is Done
    ##########################################
    ...
    ##########################################
    Channel#7 CDR is Locked to Data
    Channel#7 CDR is Locked to Reference Clock
    Channel#7 TX Calibration is Done
    Channel#7 RX Calibration is Done 
    

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