L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.2. PCI Configuration Header Registers

The Correspondence between Configuration Space Registers and the PCIe Specification lists the appropriate section of the PCI Express Base Specification that describes these registers.

Figure 49. Configuration Space Registers Address Map
Figure 50. PCI Configuration Space Registers - Byte Address Offsets and Layout

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