L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.2.1. PCI Express Avalon-MM Bridge Register Address Map

The registers included in the Avalon® -MM bridge map to a 32 KB address space. Reads to undefined addresses have unpredictable results.
Table 63.  Stratix 10 PCIe Avalon-MM Bridge Register Map
Address Range Registers
0x0050 Avalon® -MM to PCIe Interrupt Enable Register
0x0060 Avalon® -MM to PCIe Interrupt Status Register
0x0800-0x081F

Reserved.

0x0900-0x091F

Reserved.

0x1000-0x1FFF Address Translation Table for the Bursting Avalon® -MM Slave
0x3060 PCIe to Avalon® -MM Interrupt Status Register
0x3070 PCIe to Avalon® -MM Interrupt Enable Register
0x3A00–0x3A1F

Reserved

0x3B00–0x3B1F

Reserved.

0x3C00-0x3C1F PCIe Configuration Information Registers

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