L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.5. Uncorrectable Internal Error Status Register

This register reports the status of the internally checked errors that are uncorrectable. When these specific errors are enabled by the Uncorrectable Internal Error Mask register, they are forwarded as Uncorrectable Internal Errors. This register is for debug only. Only use this register to observe behavior, not to drive logic custom logic.
Table 59.  Uncorrectable Internal Error Status Register - 0xBB4This register is for debug only. It should only be used to observe behavior, not to drive custom logic.

Bits

Register Description

Reset Value

Access

[31:13]

Reserved.

0

RO

[12] Debug bus interface (DBI) access error status. 0 RW1CS

[11]

ECC error from Config RAM block.

0

RW1CS

[10]

Uncorrectable ECC error status for Retry Buffer.

0

RO

[9]

Uncorrectable ECC error status for Retry Start of the TLP RAM.

0

RW1CS

[8]

RX Transaction Layer parity error reported by the IP core.

0

RW1CS

[7]

TX Transaction Layer parity error reported by the IP core.

0

RW1CS

[6]

Internal error reported by the FPGA.

0

RW1CS

[5:4]

Reserved. 0

RW1CS

[3]

Uncorrectable ECC error status for RX Buffer Header #2 RAM.

0

RW1CS

[2]

Uncorrectable ECC error status for RX Buffer Header #1 RAM.

0

RW1CS

[1]

Uncorrectable ECC error status for RX Buffer Data RAM #2.

0

RW1CS

[0]

Uncorrectable ECC error status for RX Buffer Data RAM #1.

0

RW1CS

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