L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

1.8. PCI Express IP Core Package Layout

Intel® Stratix® 10 devices have high-speed transceivers implemented on separate transceiver tiles. The transceiver tiles are on the left and right sides of the device.

Each 24-channel transceiver L- or H- tile includes one x16 PCIe IP Core implemented in hardened logic. The following figures show the layout of PCIe IP cores in Intel® Stratix® 10 devices. Both L- and H-tiles are orange. E-tiles are green.

Figure 3.  Intel® Stratix® 10 GX/SX Devices with 4 PCIe Hard IP Cores and 96 Transceiver Channels
Figure 4.  Intel® Stratix® 10 GX/SX Devices with 2 PCIe Hard IP Cores and 48 Transceiver Channels
Figure 5.  Intel® Stratix® 10 GX/SX Devices with 2 PCIe Hard IP Cores and 48 Transceiver Channels - Transceivers on Both Sides
Figure 6.  Intel® Stratix® 10 Migration Device with 2 Transceiver Tiles and 48 Transceiver Channels
Note:
  1. Intel® Stratix® 10 migration device contains 2 L-Tiles which match Intel® Arria® 10 migration device.
Figure 7.  Intel® Stratix® 10 GX/SX Devices with 1 PCIe Hard IP Core and 24 Transceiver Channels
Figure 8.  Intel® Stratix® 10 TX Devices with 1 PCIe Hard IP Core and 144 Transceiver Channels
Note:
  1. Intel® Stratix® 10 TX Devices use a combination of E-Tiles and H-Tiles.
  2. Five E-Tiles support 57.8G PAM-4 and 28.9G NRZ backplanes.
  3. One H-Tile supports up to 28.3G backplanes and PCIe* up to Gen3 x16.
Figure 9.  Intel® Stratix® 10 TX Devices with 1 PCIe Hard IP Core and 96 Transceiver Channels
Note:
  1. Intel® Stratix® 10 TX Devices use a combination of E-Tiles and H-Tiles.
  2. Three E-Tiles support 57.8G PAM-4 and 28.9G NRZ backplanes.
  3. One H-Tile supports up to 28.3G backplanes PCIe* up to Gen3 x16..
Figure 10.  Intel® Stratix® 10 TX Devices with 2 PCIe Hard IP Cores and 72 Transceiver Channels
Note:
  1. Intel® Stratix® 10 TX Devices use a combination of E-Tiles and H-Tiles.
  2. One E-Tile support 57.8G PAM-4 and 28.9G NRZ backplanes.
  3. Two H-Tiles supports up to 28.3G backplanes PCIe* up to Gen3 x16..

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