1.8. PCI Express IP Core Package Layout
Intel® Stratix® 10 devices have high-speed transceivers implemented on separate transceiver tiles. The transceiver tiles are on the left and right sides of the device.
Each 24-channel transceiver L- or H- tile includes one x16 PCIe IP Core implemented in hardened logic. The following figures show the layout of PCIe IP cores in Intel® Stratix® 10 devices. Both L- and H-tiles are orange. E-tiles are green.
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