L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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6.1.4.2. Legacy Interrupts

Stratix® 10 PCIe Avalon-MM Bridge with DMA can generate PCIe legacy interrupt when Interrupt Disable bit 10 of Command register in Configuration Header is set to zero and MSI Enable bit of MSI Message Control register is set to zero.

Table 46.  MSI Interrupt

Signal

Direction

Description

intx_req_i

Input

Legacy interrupt request.

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