L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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1.6. Performance and Resource Utilization

The Avalon-MM Intel® Stratix® 10 variants include an Avalon-MM DMA bridge implemented in soft logic. It operates as a front end to the hardened protocol stack. The resource utilization table below shows results for the Gen1 x1 and Gen3 x8 DMA dynamically generated design examples.

The results are for the current version of the Intel® Quartus® Prime Pro Edition software. With the exception of M20K memory blocks, the numbers are rounded up to the nearest 50.

Table 5.  Resource Utilization for Intel L-/H-Tile Avalon-MM for PCI Express IP Core

Variant

Typical ALMs

M20K Memory Blocks1

Logic Registers

Gen1 x1

17,485

77

33,701
Gen3 x8 18,872 77 42,457
1 These results include the logic necessary to implement the 2, On-Chip Memories and the PCIe DMA 256-bit Controller which are included in the designs.

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