L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/26/2022
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9.1. Root Port TLP Data Control and Status Registers

The 32-bit CRA Avalon® -MM interface must be enabled for the Intel® Stratix® 10 Avalon® -MM Root Port to construct the TLPs. The CRA interface provides the four registers below for this purpose.

Table 74.  Root Port TLP Data, Control and Status Registers
Register Address Register Name Access Mode Description
0x2000 RP_TX_REG W Contains 1 dword of the TX TLP. The Application Layer keeps writing to this register to construct TX TLPs.
0x2004 RP_TX_CNTRL W

[31:3] : Reserved

[2] Type : Type of request
  • 1 : Posted request
  • 0 : Non-posted request

[1] EOP : Specifies the end of a packet.

[0] SOP : Specifies the start of a packet.

0x2008 RP_RX_REG R Contains 1 dword of the Completion TLP or Message TLP.
0x200C RP_RX_STATUS RC

[31:2] Reserved

[1] EOP : Indicates the end of data for the TLP. The Application Layer must poll this bit to determine when the final data is available.

[0] SOP : indicates that the Completion TLP or Message TLP is present.