L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

1.1. Avalon-MM Interface for PCIe

Intel® Stratix® 10 FPGAs include a configurable, hardened protocol stack for PCI Express* that is compliant with PCI Express Base Specification 3.0. This IP core combines the functionality of previous Avalon® Memory-Mapped (Avalon-MM) and Avalon-MM direct memory access (DMA) interfaces. It supports the same functionality for Intel® Stratix® 10 as the Avalon® -MM and Avalon® -MM with DMA variants for Arria® 10 devices.

The Intel L-/H-Tile Avalon-MM for PCI Express IP core using the Avalon® -MM interface removes many of the complexities associated with the PCIe protocol. It handles all of the Transaction Layer Packet (TLP) encoding and decoding, simplifying the design task. This IP core also includes optional Read and Write Data Mover modules facilitating the creation of high-performance DMA designs. Both the Avalon® -MM interface and the Read and Write Data Mover modules are implemented in soft logic.

The Intel L-/H-Tile Avalon-MM for PCI Express IP Core supports Gen1, Gen2 and Gen3 data rates and x1, x2, x4, and x8 configurations. Gen1 and Gen2 data rates are also supported with the x16 configuration.

Note: The Gen3 x16 configuration is supported by another IP core, the Intel L-/H-Tile Avalon-MM+ for PCI Express IP core. For details, refer to the Intel L- and H-tile Avalon Memory-mapped+ IP for PCI Express User Guide.
Figure 1.  Intel® Stratix® 10 PCIe IP Core Variant with Avalon® -MM Interface
Table 1.  PCI Express Data Throughput

The following table shows the theoretical link bandwidth of a PCI Express link for Gen1, Gen2, and Gen3 for 1, 2, 4, 8, and 16 lanes excluding overhead. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. The protocol specifies 2.5 giga-transfers per second (GT/s) for Gen1, 5.0 GT/s for Gen2, and 8.0 GT/s for Gen3. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead. Gen3 uses 128b/130b encoding which an overhead of 1.54%. The following table shows the actual usable data bandwidth in gigabits per second (Gbps). The encoding and decoding overhead has been removed.

Link Width
×1 ×2 ×4 ×8 ×16

PCI Express Gen1 (2.5 Gbps)

2

4

8

16

32

PCI Express Gen2 (5.0 Gbps)

4

8

16

32

64

PCI Express Gen3 (8.0 Gbps)

7.87

15.75

31.5

63

Not available in current release

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