L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
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5.2. Simulation

The Intel® Quartus® Prime Pro Edition software optionally generates a functional simulation model, a testbench or design example, and vendor-specific simulator setup scripts when you generate your parameterized PCI Express* IP core. For Endpoints, the generation creates a Root Port BFM.

Note: Root Port example design generation is not supported in this release of Intel® Quartus® Prime Pro Edition.

The Intel® Quartus® Prime Pro Edition supports the following simulators.

Table 27.  Supported Simulators
Vendor Simulator Version Platform
Aldec Active-HDL * 10.3 Windows
Aldec Riviera-PRO * 2016.10 Windows, Linux
Cadence Incisive Enterprise * (NCSim*) 15.20 Linux
Cadence Xcelium* Parallel Simulator 17.04.014 Linux
Mentor Graphics ModelSim PE* 10.5c Windows
Mentor Graphics ModelSim SE* 10.5c Windows, Linux
Mentor Graphics QuestaSim* 10.5c Windows, Linux
Synopsys VCS*/VCS MX* 2016,06-SP-1 Linux
Note: The Intel testbench and Root Port BFM provide a simple method to do basic testing of the Application Layer logic that interfaces to the PCIe IP variation. This BFM allows you to create and run simple task stimuli with configurable parameters to exercise basic functionality of the example design. The testbench and Root Port BFM are not intended to be a substitute for a full verification environment. Corner cases and certain traffic profile stimuli are not covered. To ensure the best verification coverage possible, Intel suggests strongly that you obtain commercially available PCI Express verification IP and tools, or do your own extensive hardware testing or both.

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