L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
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After fetching multiple descriptor entries from the Descriptor Table in the PCIe* system memory, the Descriptor Controller uses its Avalon® -ST Descriptor source interface to transfer 160-bit Descriptors to the Read or Write DMA Data Movers.

Table 35.   Avalon® -ST Descriptor Sink InterfaceThis interface sends instructions from Descriptor Controller to Read DMA Engine.

Signal Name

Direction

Description

rd_ast_rx_data_i[159:0]

Input

Specifies the descriptors for the Read DMA module. Refer to DMA Descriptor Format table below for bit definitions.

rd_ast_rx_valid_i

Input

When asserted, indicates that the data is valid.

rd_ast_rx_ready_o

Output

When asserted, indicates that the Read DMA read module is ready to receive a new descriptor.

The ready latency is 1 cycle. Consequently, interface can accept data 1 cycle after ready is asserted.
Table 36.   Avalon® -ST Descriptor Sink Interface This interface sends instructions from Descriptor Controller to Write DMA Engine.

Signal Name

Direction

Description

wr_ast_rx_data_i[159:0]

Input

Specifies the descriptors for the Write DMA module. Refer to DMA Descriptor Format table below for bit definitions.

wr_ast_rx_valid_i

Input

When asserted, indicates that the data is valid.

wr_ast_rx_ready_o

Output

When asserted, indicates that the Write DMA module engine is ready to receive a new descriptor. The ready latency for this signal is 1 cycle. Consequently, interface can accept data 1 cycle after ready is asserted.

 

Descriptor Table Format

Descriptor table entries include the source address, the destination address, the size, and the descriptor ID. Each descriptor is padded with zeros to 256-bits (32 bytes) to form an entries in the table.
Table 37.  DMA Descriptor Format

Bits

Name

Description

[31:0]

Source Low Address

Low-order 32 bits of the DMA source address. The address boundary must align to the 32 bits so the 2 least significant bits are 2'b00. For the Read Data Mover module, the source address is the PCIe domain address. For the Write Data Mover module, the source address is the Avalon-MM domain address.

[63:32]

Source High Address

High-order 32 bits of the source address.

[95:64]

Destination Low Address

Low-order 32 bits of the DMA destination address. The address boundary must align to the 32 bits so the 2 least significant bits have the value of 2'b00. For the Read Data Mover module, the destination address is the Avalon-MM domain address. For the Write Data Mover module, the destination address is the PCIe domain address.

[127:96]

Destination High Address

High-order 32 bits of the destination address.

[145:128]

DMA Length

Specifies the number of dwords to transfer. The length must be greater than 0. The maximum length is 1 MB - 4 bytes.

[153:146]

DMA Descriptor ID

Unique 7-bit ID for the descriptor. Status information returns with the same ID.

[159:154]

Reserved

Avalon -ST Descriptor Status Sources

Read Data Mover and Write Data Mover modules report status to the Descriptor Controller on the rd_dma_tx_data_o[31:0] or wr_dma_tx_data_o[31:0] bus when a descriptor completes successfully.

The following table shows the mappings of the triggering events to the DMA descriptor status bus:

Table 38.  DMA Status Bus

Bits

Name

Description

[31:9]

Reserved

[8]

Done

When asserted, a single DMA descriptor has completed successfully.

[7:0] Descriptor ID The ID of the descriptor whose status is being reported.

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