L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

7.1.1. Register Access Definitions

This document uses the following abbreviations when describing register access.
Table 53.  Register Access AbbreviationsSticky bits are not initialized or modified by hot reset or function-level reset.
Abbreviation Meaning
RW Read and write access
RO Read only
WO Write only
RW1C Read write 1 to clear
RW1CS Read write 1 to clear sticky
RWS Read write sticky

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