L-tile and H-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683667
Date 11/11/2021
Public
Document Table of Contents

6.1.1.1.2. Read Descriptor Controller Avalon-MM Master interface

The Read Descriptor Controller Avalon-MM master interface drives the non-bursting Avalon-MM slave interface. The Read Descriptor Controller uses this interface to write descriptor status to the PCIe domain and possibly to MSI when MSI messages are enabled. This Avalon-MM master interface is only available for variants with the internally instantiated Descriptor Controller.

By default MSI interrupts are enabled. You specify the Number of MSI messages requested on the MSI tab of the parameter editor. The MSI Capability Structure is defined in Section 6.8.1 MSI Capability Structure of the PCI Local Bus Specification.

Table 30.  Read Descriptor Controller Avalon-MM Master interface

Signal Name

Direction

Description

rd_dcm_address_o[63:0]

Output

Specifies the descriptor status table or MSI address.

rd_dcm_byte_enable_o[3:0]

Output

Specifies which data bytes are valid.

rd_dcm_read_data_valid_i

Input

When asserted, indicates that the read data is valid.

rd_dcm_read_data_i[31:0]

Input

Specifies the read data of the descriptor status table entry addressed.

rd_dcm_read_o

Output

When asserted, indicates a read transaction. Currently, this is a write-only interface so that this signal never asserts.

rd_dcm_wait_request_i

Input

When asserted, indicates that the connected Avalon-MM slave interface is busy and cannot accept a transaction.

rd_dcm_write_data_o[31:0]

Output

Specifies the descriptor status or MSI data..

rd_dcm_write_o

Output

When asserted, indicates a write transaction.

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